In order to realize accurate bilinear transformation from s- to z-domain, a novel switched- capacitor configuration is proposed in the light of principles of dual-rate sampling and charge conservation, which has also been used for building a 5th-order elliptic lowpass filter. The filter is simulated and measured in typical 0.34 μm/3.3 V Si CMOS process models, special full differential operational amplifiers and CMOS transfer gate switches, which achieves 80 MHz sampling rate, 17.8 MHz cutoff frequency, 0.052 dB maximum passband ripple, 42.1 dB minimum stopband attenuation and 74 mW quiescent power dissipation. At the same time, the dual-rate sampling topology breaks the traditional restrictions of filter introduced by unit-gain bandwidth and slew rate of operational amplifiers and also improves effectively their performances in high-frequency applications. It has been applied for the design of an anti-alias filter in analog front-end of video decoder IC with 15 MHz signal frequency yet.
[1]
Masayuki Miyamoto,et al.
Embedded anti-aliasing in switched-capacitor ladder filters
,
2001,
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).
[2]
Masayoshi Tomizuka,et al.
Modeling, analysis and design tools for dual-rate systems
,
2002,
Proceedings of the 2002 American Control Conference (IEEE Cat. No.CH37301).
[3]
Joyce Cheuk,et al.
CMOS Sample-and-Hold Circuits
,
2001
.
[4]
Un-Ku Moon.
CMOS high-frequency switched-capacitor filters for telecommunication applications
,
2000,
IEEE Journal of Solid-State Circuits.