Managing Within Budget Overlay Metrology Accuracy in a 0.18 µm Copper Dual Damascene Process

As overlay budgets shrink with design rules, the importance of overlay metrology accuracy increases. We have investigated the overlay accuracy of a 0.18 μm design rule copper dual damascene process by comparing the overlay metrology results at the after develop (DI) and after etch (FI) stages. The comparisons were done on five process layers on production wafers, while ensuring that the DI and FI measurements were always done on the same wafer. In addition, we measured the in-die overlay on one of the process layers (poly gate) using a CD SEM, and compared the results to the optical overlay metrology in the scribe-line. We found that a serious limitation to in-die overlay calibration was the lack of suitable structures measurable by CD SEM. We will present quantitative results from our comparisons, as well as a recommendation for incorporating CD SEM-measurable structures in the chip area in future reticle designs.