Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability
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Francky Catthoor | Wim Dehaene | Said Hamdioui | Mottaqiallah Taouil | Praveen Raghavan | Pieter Weckx | Stefan Cosemans | Innocent Agbo
[1] G. Groeseneken,et al. Atomistic approach to variability of bias-temperature instability in circuit simulations , 2011, 2011 International Reliability Physics Symposium.
[2] Michael Nicolaidis,et al. Reliability challenges of real-time systems in forthcoming technology nodes , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[3] B. Kaczer,et al. Analytic modeling of the bias temperature instability using capture/emission time maps , 2011, 2011 International Electron Devices Meeting.
[4] A.B. Kahng,et al. Impact of Guardband Reduction On Design Outcomes: A Quantitative Approach , 2009, IEEE Transactions on Semiconductor Manufacturing.
[5] G. Groeseneken,et al. Time and workload dependent device variability in circuit simulations , 2011, 2011 IEEE International Conference on IC Design & Technology.
[6] Robert C. Aitken,et al. Analytical model for TDDB-based performance degradation in combinational logic , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[7] Francky Catthoor,et al. Scaling of BTI reliability in presence of time-zero variability , 2014, 2014 IEEE International Reliability Physics Symposium.
[8] R. Degraeve,et al. Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.
[9] Mehdi Kamal,et al. An efficient reliability simulation flow for evaluating the hot carrier injection effect in CMOS VLSI circuits , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).
[10] Francky Catthoor,et al. Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates , 2014, IEEE Transactions on Device and Materials Reliability.
[11] Stefan Cosemans,et al. Variability-Aware Design of Low Power SRAM Memories (Variabiliteitsbewust ontwerp van SRAM geheugens met een zeer laag energieverbruik) , 2009 .
[12] Jiajing Wang,et al. Statistical modeling for the minimum standby supply voltage of a full SRAM array , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.
[13] Ying Chen,et al. Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).
[14] N. Horiguchi,et al. Response of a single trap to AC negative Bias Temperature stress , 2011, 2011 International Reliability Physics Symposium.
[15] W. Dehaene,et al. A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability , 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.
[16] Marcel J. M. Pelgrom,et al. Matching properties of MOS transistors , 1988, ESSCIRC '88: Fourteenth European Solid-State Circuits Conference.
[17] Mehdi Baradaran Tahoori,et al. Aging mitigation in memory arrays using self-controlled bit-flipping technique , 2015, The 20th Asia and South Pacific Design Automation Conference.
[18] Jörg E. Vollrath. Signal margin analysis for DRAM sense amplifiers , 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.
[19] T. DeMassa,et al. Threshold voltage variations with temperature in MOS transistors , 1971 .
[20] Sachin S. Sapatnekar,et al. Overcoming Variations in Nanometer-Scale Technologies , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
[21] T. Grasser,et al. Defect-based methodology for workload-dependent circuit lifetime projections - Application to SRAM , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).