Fully compatible novel SNONOS structure for improved electrical performance in NAND Flash memories

Abstract A fully integrated gate stack structure with an additional stoichiometric silicon nitride layer in the control oxide referred to as “SNONOS” is used to improve the electrical performance of nitride-based memories. The process is completely compatible with conventional silicon processes. By employing the new structure, the detrimental “back-tunneling” effect is suppressed without sacrificing device capacitance. Thus, a threshold voltage improvement of approximately 1.2 V is observed for the erase state. Retention for devices with similar erase performance is also improved with the SNONOS structure. Further mitigation of the “back-tunneling” effect is observed for devices with high work function gate material.