Safe programming of PLC using formal verification methods

The Corporate Research Center of ALCATEL (Marcoussis, France) and two laboratories of the Ecole Normale Superieure (Cachan, France) have been involved since March 1998 in a research project in the field of formal verification of Programmable Logic Controllers (PLC) programs. The Sequential Function Chart (SFC), Ladder Diagram (LD) and Structured Text (ST) languages have been chosen among the five languages defined in the IEC 61131-3 standard. The aim of this project is the development of methods and algorithms enabling the designer to decide if the PLC program verifies the safety, liveness and time properties specified in the requirements.

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