A Reconfigurable TAF-DPS Frequency Synthesizer on FPGA Achieving 2 ppb Frequency Granularity and Two-Cycle Switching Speed

Frequency synthesizer is a key component used in electronic systems. Two important features for judging its performance are frequency granularity and frequency switching speed. In this paper, a synthesizer built on the principle of time-average-frequency (TAF) is implemented on an FPGA system. The synthesizer is constructed entirely on the FPGA's configurable elements. The granularity is measured as 2 ppb; the frequency switching speed is experimentally illustrated as two cycles. The configuration of the synthesizer can be adjusted in the field for accommodating various performance versus cost scenarios. The aim of this paper is to provide a field-programmable frequency generator as a handy tool to FPGA users, to enable user create innovations at application level. The key contributions are the 2 ppb frequency granularity and the reconfigurable implementation of the time-average-frequency direct period synthesis (TAF-DPS) synthesizer on FPGA.

[1]  Liming Xiu,et al.  Flying-Adder Fractional Divider Based Integer-N PLL: 2nd Generation FAPLL as On-Chip Frequency Generator for SoC , 2013, IEEE Journal of Solid-State Circuits.

[2]  Kofi A. A. Makinwa,et al.  A Thermistor-Based Temperature Sensor for a Real-Time Clock With $\pm$ 2 ppm Frequency Stability , 2015, IEEE Journal of Solid-State Circuits.

[3]  Bo Zhao,et al.  A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[4]  Wei Wang,et al.  A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  Yu Wang,et al.  A 1.9 GHz ADPLL with 130 reference cycles settling time in 0.18 μm CMOS technology , 2013 .

[6]  Liming Xiu,et al.  An architecture of high-performance frequency and phase synthesis , 2000, IEEE Journal of Solid-State Circuits.

[7]  Ching-Che Chung,et al.  A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Jason Wei,et al.  A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators , 2015, IEEE Journal of Solid-State Circuits.

[9]  Shey-Shi Lu,et al.  A Single-VCO Fractional-$N$ Frequency Synthesizer for Digital TV Tuners , 2007, IEEE Transactions on Industrial Electronics.

[10]  Liming Xiu A Fast and Power–Area-Efficient Accumulator for Flying-Adder Frequency Synthesizer , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Bin Wu,et al.  A Novel Hardware-Based All-Digital Phase-Locked Loop Applied to Grid-Connected Power Converters , 2011, IEEE Transactions on Industrial Electronics.

[12]  Kofi A. A. Makinwa,et al.  A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator , 2015, IEEE Journal of Solid-State Circuits.

[13]  Hyung Seok Kim,et al.  A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique , 2013, IEEE Journal of Solid-State Circuits.

[14]  Chia-Yu Yao,et al.  A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase–Frequency-Error Compensation , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Liming Xiu The concept of time-average-frequency and mathematical analysis of flying-adder frequency synthesis architecture , 2008, IEEE Circuits and Systems Magazine.

[16]  Liming Xiu,et al.  A "flying-adder" architecture of frequency and phase synthesis with scalability , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[17]  Liming Xiu Nanometer Frequency Synthesis Beyond the Phase-Locked Loop: Xiu/Nanometer Frequency Synthesis , 2012 .