A VLSI-IP Module Design for Implementing Multi-hash Function

This work presents a VLSI-IP module design for implementing multi-hash function, applied to an authentication module design for network security processor. On the basis of implementing hash function such as SHA-1 and CHI, by using iteration technology, this module supports not only keyed-hashing for message authentication such as HMAC-SHA-1 and HMAC-CHI-160,but also generating MASTER-KEY and KEY-BLOCK in SSL(Security Socket Layer) protocol. This module was designed with SMIC 0.13μm CMOS technology occuping 0.61mm2 with critical path of 4.56ns, the implementation result gives a throughput of 1.82Gb/s for SHA-1.