Over the last years, many new materials have been introduced in advanced CMOS processes in order to continue the scaling and further improve the device performance. As a key example, the introduction of deposited hafnium-based gate dielectrics together with metal gates as a replacement for the thermally grown SiO2 and poly-Si electrode was a major step towards a better electrostatic control of the channel region (Equivalent Oxide Thickness downscaling) while maintaining the power consumption under control (gate leakage reduction). In the next generation technology nodes like for sub-2x-nm, even bigger hurdles will have to be taken since the performance is no longer increasing with the scaling trend and a performance gap seems to arise. To keep up the system performance, engineering at the channel level is needed. The idea is then to allocate space for high-performing high-mobility materials such as Germanium and III-V compound semiconductors.