Energy Optimization for Multi-level Cell STT-MRAM Using State Remapping

Multi-level Cell Spin-Transfer Torque Magnetic RAM (MLC STT-MRAM), is emerging as a promising candidate to build L2 cache. However, the high write energy impedes the adoption of MLC STT-MRAM. In this paper, we focus on reducing the write energy consumption. For a 2-bit STT-MRAM cell, the energy consumption of flipping the left bit is greater than that of flipping the right bit. Beside, writing state '01' and state '10' consumes more energy than writing states '00' and '11'. To reduce the energy consumption during MLC STT-MRAM write operations, we propose an encoding scheme to minimize the number of the left bit flips and reduce the write count of states '01' and '10' by exchanging two states with different left bit, such as states '00' and '10', when exchanging two states can reduce the total write energy consumption of a cache line. The main idea of this scheme is state remapping. The experimental results show that the encoding scheme reduces 12.17% write energy consumption on average and up to 27.58% based on the complex write scheme.

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