A low power BIST scheme based on block encoding
暂无分享,去创建一个
Tian Chen | Wei Wang | Fuji Ren | Xishan Zhang | Liuyang Zheng | Hao Chang
[1] Nur A. Touba,et al. LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Liang Hua. A Scheme of LFSR Reseeding Based on Dividing Parity Bits of Test Cubes , 2007 .
[3] Rohit Kapur,et al. Bounded Adjacent Fill for Low Capture Power Scan Testing , 2008, 26th IEEE VLSI Test Symposium (vts 2008).
[4] Sheng Zhang,et al. On finding consecutive test vectors in a random sequence for energy-aware BIST design , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.
[5] Patrick Girard,et al. Low power BIST design by hypergraph partitioning: methodology and architectures , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[6] Bashir M. Al-Hashimi,et al. Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[7] Sandeep K. Gupta,et al. ATPG for heat dissipation minimization during test application , 1994, Proceedings., International Test Conference.
[8] Ali Afzali-Kusha,et al. Mixed RL-Huffman encoding for power reduction and data compression in scan test , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[9] Nur A. Touba,et al. Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.
[10] Yervant Zorian,et al. A distributed BIST control scheme for complex VLSI devices , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.
[11] Bernard Courtois,et al. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers , 1995, IEEE Trans. Computers.
[12] Nur A. Touba,et al. Controlling peak power during scan testing , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).
[13] Sandeep K. Gupta,et al. DS-LFSR: a new BIST TPG for low heat dissipation , 1997, Proceedings International Test Conference 1997.
[14] Kozo Kinoshita,et al. A new ATPG method for efficient capture power reduction during scan testing , 2006, 24th IEEE VLSI Test Symposium.
[15] Krishnendu Chakrabarty,et al. Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[16] Sybille Hellebrand,et al. A hybrid coding strategy for optimized test data compression , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[17] Patrick Girard,et al. A modified clock scheme for a low power BIST test pattern generator , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.
[18] Wang Wei,et al. A Test Compression Scheme Based on LFSR Reseeding and Optimized Coding , 2012 .