A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection

A fully differential comparator is described. It uses a switched-capacitor differencing circuit that provides common-mode rejection. The comparator has been tested by building a 3-b flash analog-to-digital converter (ADC) in a 2-/spl mu/m CMOS process. With a supply voltage of 3.3 V, a sampling rate of 25 MHz, and full-scale sinusoidal inputs up to 7 MHz, the signal-to-distortion ratio of the ADC when the input is single ended is about 1-2 dB less than when the input is differential. In a 2-/spl mu/m CMOS process, the comparator occupies 0.25 mm/sup 2/ and dissipates 1.05 mW.

[1]  Behzad Razavi,et al.  A 12-b 5-Msample/s two-step CMOS A/D converter , 1992 .

[2]  T. Yamada,et al.  A CMOS 40 MHz 8 b 105 mW two-step ADC , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[3]  S. H. Lewis,et al.  A pipelined 5-Msample/s 9-bit analog-to-digital converter , 1987 .

[4]  P.R. Gray,et al.  A MOS switched-capacitor instrumentation amplifier , 1982, IEEE Journal of Solid-State Circuits.

[5]  S. Hosotani,et al.  An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption , 1990 .

[6]  Jieh-Tsorng Wu,et al.  A 100-MHz pipelined CMOS comparator , 1988 .

[7]  M. K. Mayes,et al.  A multistep A/D converter family with efficient architecture , 1989 .

[8]  J. Doernberg,et al.  A 10-bit 5-Msample/s CMOS two-step flash ADC , 1989 .

[9]  M. F. Tompsett,et al.  A 10-b 15-MHz CMOS recycling two-step A/D converter , 1990 .

[10]  L. R. Carley,et al.  An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC , 1995 .

[11]  A. Dingwall,et al.  An 8-MHz CMOS subranging 8-bit A/D converter , 1985, IEEE Journal of Solid-State Circuits.

[12]  Stephen H. Lewis,et al.  A switched-capacitor differencing circuit with common-mode rejection for fully differential comparators , 1993, Proceedings of 36th Midwest Symposium on Circuits and Systems.

[13]  Paul R. Gray,et al.  A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS , 1991 .

[14]  Toshio Kumamoto,et al.  A 10 bit 20 MS/s 3 V supply CMOS A/D converter , 1994 .