Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters
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Arjuna Madanayake | Leonard T. Bruton | Thushara K. Gunaratne | L. Bruton | A. Madanayake | T. Gunaratne
[1] Leonard T. Bruton,et al. Reducing the computational complexity of narrowband 2D fan filters using shaped 2D window functions , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[2] Andreas Antoniou,et al. Realization of multidimensional GIC digital filters , 1990 .
[3] A.H.M. van Roermund,et al. Analog calibration of channel mismatches in time-interleaved ADCs , 2009 .
[4] A. Fettweis. Wave digital filters: Theory and practice , 1986, Proceedings of the IEEE.
[5] Ryuji Kohno,et al. Frequency selective broadband beamforming using 2D digital filters , 2000, VTC2000-Spring. 2000 IEEE 51st Vehicular Technology Conference Proceedings (Cat. No.00CH37026).
[6] Arjuna Madanayake,et al. A Systolic Array 2-D IIR Broadband RF Beamformer , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.
[7] Graham A. Jullien,et al. High-speed signal processing using systolic arrays over finite rings , 1988, IEEE J. Sel. Areas Commun..
[8] Leonard T. Bruton,et al. 3-D IIR filtering using decimated DFT-polyphase filter bank structures , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.
[9] A. van Ardenne. Concepts of the Square Kilometre Array; toward the new generation radio telescopes , 2000 .
[10] E.C. Fear,et al. Tissue Sensing Adaptive Radar for Breast Cancer Detection—Experimental Investigation of Simple Tumor Models , 2005, IEEE Transactions on Microwave Theory and Techniques.
[11] Håkan Johansson,et al. Time-interleaved analog-to-digital converters: status and future directions , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[12] Keshab K. Parhi,et al. Synthesis of folded multi-dimensional DSP systems , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).
[13] P. P. Vaidyanathan,et al. Theory and design of two-dimensional filter Banks: A review , 1996, Multidimens. Syst. Signal Process..
[14] Nanyan Y. Wang,et al. Analysis of beamformer configurations for DS-CDMA systems , 2005, IEEE Transactions on Signal Processing.
[15] Len T. Bruton,et al. On the limitations of narrow 2D fan filters speech processing , 2003, 2003 IEEE Pacific Rim Conference on Communications Computers and Signal Processing (PACRIM 2003) (Cat. No.03CH37490).
[16] A. Brown,et al. Space Navigation with Digital Beam Steering GPS Receiver Technology , 2003 .
[17] A. Fettweis,et al. Some principles of designing digital filters imitating classical filter structures , 1971, IEEE Transactions on Circuit Theory.
[18] Naresh R. Shanbhag,et al. An improved systolic architecture for 2-D digital filters , 1991, IEEE Trans. Signal Process..
[19] H.L.P. Madanayake,et al. Low-complexity distributed parallel processor for 2D IIR broadband beam plane-wave filters , 2007, Canadian Journal of Electrical and Computer Engineering.
[20] Synthesis of 3-D lossless first-order one ports with lumped elements , 1989 .
[21] Alison Brown,et al. REPROGRAMMABLE, DIGITAL BEAM STEERING GPS RECEIVER TECHNOLOGY FOR ENHANCED SPACE VEHICLE OPERATIONS , 2002 .
[22] W.S. Song,et al. High-performance low-power bit-level systolic array signal processor with low-threshold dynamic logic circuits , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).
[23] K. Bowman,et al. Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance , 2000, IEEE Journal of Solid-State Circuits.
[24] B. Wooley,et al. A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling , 2003, IEEE J. Solid State Circuits.
[25] Richard T. Schilizzi,et al. The Square Kilometre Array , 2009, Proceedings of the IEEE.
[26] A. Madanayake,et al. UWB beamforming using digital 2D IIR frequency-planar filters , 2008, 2008 IEEE Antennas and Propagation Society International Symposium.
[27] Keshab K. Parhi,et al. VLSI digital signal processing systems , 1999 .
[28] Keshab K. Parhi,et al. Area-power-time efficient pipeline-interleaved architectures for wave digital filters , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).
[29] Fredrik Gustafsson,et al. Analysis of mismatch noise in randomly interleaved ADC system , 2003, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)..
[30] John D. Bunton. Ska Correlator Advances , 2004 .
[31] S. Y. Kung. VLSI array processors: designs and applications , 1988, 1988., IEEE International Symposium on Circuits and Systems.
[32] Leonard T. Bruton. A 3D polyphase-DFT cone filter bank for broad band plane wave filtering , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[33] Keshab K. Parhi,et al. Look-ahead computation: Improving iteration bound in linear recursions , 1987, ICASSP '87. IEEE International Conference on Acoustics, Speech, and Signal Processing.
[34] A. Fettweis,et al. Suppression of parasitic oscillations in multidimensional wave digital filters , 1978 .
[35] M.N.S. Swamy,et al. Realization of resistively terminated two-variable lossless ladder networks , 1982 .
[36] Anastasios N. Venetsanopoulos,et al. Fast Implementation of 3-D Digital Filters Via Systolic Array Processors , 1997, Multidimens. Syst. Signal Process..
[37] C. Rader,et al. VLSI systolic arrays for adaptive nulling , 1996 .
[38] Jae-Jin Lee,et al. Implementation of the super-systolic array for convolution , 2003, ASP-DAC '03.
[39] M.N.S. Swamy,et al. Determination of quantization error in two-dimensional digital filters , 1981, Proceedings of the IEEE.
[40] Leonard T. Bruton,et al. Practical-BIBO stability of n-dimensional discrete systems , 1983 .
[41] A. Antoniou,et al. Multi-dimensional wave digital filters based on the concept of the GIC , 1989, IEEE International Symposium on Circuits and Systems,.
[42] Arnab K. Shaw,et al. Pipelined recursive digital filters: a general look-ahead scheme and optimal approximation , 1999 .
[43] Arjuna Madanayake,et al. A Speed-Optimized Systolic Array Processor Architecture for Spatio-Temporal 2-D IIR Broadband Beam Filters , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[44] Chein-Wei Jen,et al. The designs of two-level pipelined systolic arrays for recursive digital filters with maximum throughput rate , 1991, 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers.
[45] Keshab K. Parhi. Pipelining in algorithms with quantizer loops , 1991 .
[46] Arjuna Madanayake,et al. FPGA architectures for real-time 2D/3D FIR/IIR plane wave filters , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[47] M.N.S. Swamy,et al. Finite word length effect and stability of multidimensional digital filters , 1981, Proceedings of the IEEE.
[48] R. Grondin,et al. Dynamic computational blocks for bit-level systolic arrays , 1994 .
[49] Pramod Kumar Meher,et al. Hardware-Efficient Systolization of DA-Based Calculation of Finite Digital Convolution , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.
[50] Arjuna Madanayake. FPGA architectures for 2D/3D digital filters , 2004 .
[51] C. M. Rader,et al. VLSI systolic arrays for adaptive nulling [radar] , 1996, IEEE Signal Process. Mag..
[52] Leonard T. Bruton,et al. High-speed systolic ladder structures for multidimensional recursive digital filters , 1996, IEEE Trans. Signal Process..
[53] Arjuna Madanayake,et al. An FPGA architecture for real-time polyphase 2D FIR double-trapezoidal plane-wave filters , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.
[54] M. A. Sid-Ahmed,et al. A switched-capacitor implementation for video rate 2-D filters , 1993 .
[55] Keshab K. Parhi,et al. Finite word effects in pipelined recursive filters , 1991, IEEE Trans. Signal Process..
[56] Leonard T. Bruton,et al. Three-dimensional image processing using the concept of network resonance , 1985 .
[57] A. Fettweis. Pseudo-passivity, sensitivity, and stability of wave digital filters , 1972 .
[58] Jenq-Neng Hwang,et al. Wavefront Array Processors-Concept to Implementation , 1987, Computer.
[59] Leonard T. Bruton,et al. A novel low-complexity spatio-temporal ultra wide-angle polyphase cone filter bank applied to sub-pixel motion discrimination , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[60] Arjuna Madanayake,et al. A real-time systolic array processor implementation of two-dimensional IIR filters for radio-frequency smart antenna applications , 2008, 2008 IEEE International Symposium on Circuits and Systems.
[61] Steven W. Ellingson. a Dsp Engine for a 64-ELEMENT Array , 2000 .
[62] T. Itoh,et al. A smart antenna receiver array using a single RF channel and digital beamforming , 2002, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).
[63] Keshab K. Parhi,et al. Pipelined VLSI recursive filter architectures using scattered look-ahead and decomposition , 1988, ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing.
[64] Pramod Kumar Meher. Systolic Designs for DCT Using a Low-Complexity Concurrent Convolutional Formulation , 2006, IEEE Transactions on Circuits and Systems for Video Technology.
[65] Jerahmie William Radder. Implementation of a High Throughput Variable Decimation Pane Filter Using the Xilinx System Generator , 2003 .
[66] Joseph Wing-Kau Lam. Computer-aided analysis of wave digital filters and comparison of the effects of quantization on digital filters , 1980 .
[67] Joseph Lazio. The Square Kilometer Array , 2008 .
[68] Wim van Cappellen,et al. Aperture Arrays for the SKA: Dense or Sparse? , 2006, astro-ph/0611160.
[69] Maher A. Sid-Ahmed,et al. Hardware realization of a 2D IIR semisystolic filter with application to real-time homomorphic filtering , 1993, IEEE Trans. Circuits Syst. Video Technol..
[70] Zhi Ning Chen,et al. Ultra Wideband Wireless Communication: Arslan/Ultra Wideband Wireless Communication , 2006 .
[71] Leonard T. Bruton,et al. Design of stable two‐dimensional analogue and digital filters with applications in image processing , 1979 .
[72] David A. Johns,et al. Time-interleaved oversampling convertors , 1993 .
[73] Bryan Butler,et al. The Expanded Very Large Array , 2009, Proceedings of the IEEE.
[74] Keshab K. Parhi,et al. A novel systolic array structure for DCT , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.
[75] Qi An,et al. Calibration of Time-Skew Error in a M-Channel Time-Interleaved Analog-to-Digital Converters , 2007, 2007 8th International Conference on Electronic Measurement and Instruments.
[76] Arjuna Madanayake,et al. A Systolic-Array Architecture for First-Order 3-D IIR Frequency-Planar Filters , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[77] Matej Zajc,et al. Array processors for DSP: implementation considerations , 2000, 2000 10th Mediterranean Electrotechnical Conference. Information Technology and Electrotechnology for the Mediterranean Countries. Proceedings. MeleCon 2000 (Cat. No.00CH37099).
[78] Keshab K. Parhi,et al. Concurrent architectures for two-dimensional recursive digital filtering , 1989 .
[79] W. S. Song,et al. One trillion operations per second on-board VLSI signal processor for Discoverer II space based radar , 2000, 2000 IEEE Aerospace Conference. Proceedings (Cat. No.00TH8484).
[80] Leonard T. Bruton,et al. Beamforming of Broad-Band Bandpass Plane Waves Using Polyphase 2-D FIR Trapezoidal Filters , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[81] Maher A. Sid-Ahmed. A systolic realization for 2-D digital filters , 1989, IEEE Trans. Acoust. Speech Signal Process..
[82] P. P. Vaidyanathan,et al. Fundamentals of multidimensional multirate digital signal processing , 1990 .
[83] Basant Kumar Mohanty,et al. High throughput and low-latency implementation of bit-level systolic architecture for 1D and 2D digital filters , 1999 .
[84] Luca Fanucci,et al. Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters , 2009, IEICE Trans. Electron..
[85] Yuejin Zhang,et al. Applications of 3-D LCR networks in the design of 3-D recursive filters for processing image sequences , 1994, IEEE Trans. Circuits Syst. Video Technol..
[86] Zhijian Hu,et al. A bit-level systolic 2D-IIR digital filter without feedback , 1996, Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers.
[87] Pramod Kumar Meher,et al. Design of a fully-pipelined systolic array for flexible transposition-free VLSI of 2-D DFT , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.
[88] Franco Maloberti,et al. Gain and offset mismatch calibration in time-interleaved multipath A/D sigma-delta modulators , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.
[89] W. S. Song. VLSI bit-level systolic array for radar front-end signal processing , 1994, Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers.
[90] H. H. Loomis,et al. New approach to clustered look-ahead pipelined IIR digital filters , 1995 .
[91] C. Fowler,et al. Assessment of ultra-wideband (UWB) technology , 1990, IEEE Aerospace and Electronic Systems Magazine.
[92] Leonard T. Bruton,et al. Design of stable symmetric and non-symmetric half-plane digital recursive filters , 1979, ICASSP.
[93] M. Omair Ahmad,et al. Realization of a class of two-dimensional analog ladders with applications to wave digital filters , 1978, ICASSP.
[94] W. Black,et al. Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[95] Ryuji Kohno,et al. Ultra Wideband Signals and Systems in Communication Engineering: Ghavami/Ultra Wideband Signals and Systems in Communication Engineering , 2004 .
[96] L.T. Bruton,et al. UWB Beamforming Using 2-D Beam Digital Filters , 2009, IEEE Transactions on Antennas and Propagation.