An efficient delay test generation system for combinational logic circuits

This paper presents an efficient delay test generation system for combinational logic circuits. Delay testing problems are divided into gross delay fault testing and small delay fault testing in order to explore the trade-off between the levels of delay testing effort and the confidence levels of proper system operation. Complete automatic test pattern generation algorithms are proposed for both gross delay faults and small delay faults. Especially for the small delay fault test generation, new search space enumeration techniques are employed so as to bias the search space such that a delay test for relatively long paths can be found. Also a novel timing analysis method via functionality check is presented for delay test generation. Finally, complete test results are demonstrated for both gross delay faults and small delay faults on several benchmark circuits.

[1]  Dov Harel,et al.  A linear algorithm for finding dominators in flow graphs and related problems , 1985, STOC '85.

[2]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[3]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[4]  M. Ray Mercer,et al.  A Deterministic Approach to Adjacency Testing for Delay Faults , 1989, 26th ACM/IEEE Design Automation Conference.

[5]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[6]  Sudhakar M. Reddy,et al.  On the detection of delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[7]  Barry K. Rosen,et al.  Delay test generation. I. Concepts and coverage metrics , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[8]  M. Ray Mercer,et al.  Statistical delay fault coverage and defect level for delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[9]  Barry K. Rosen,et al.  Delay test generation. II. Algebra and algorithms , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[10]  M. R. Mercer,et al.  A statistical model for delay-fault testing , 1989, IEEE Design & Test of Computers.

[11]  Jacob Savir,et al.  Random Pattern Testability of Delay Faults , 1988, IEEE Trans. Computers.

[12]  Robert B. Hitchcock,et al.  Timing Analysis of Computer Hardware , 1982, IBM J. Res. Dev..

[13]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[14]  John A. Waicukauski,et al.  Transition Fault Simulation by Parallel Pattern Single Fault Propagation , 1986, International Test Conference.

[15]  Robert A. Rasmussen,et al.  Delay test generation , 1977, DAC '77.

[16]  M. Ray Mercer,et al.  A Topological Search Algorithm for ATPG , 1987, 24th ACM/IEEE Design Automation Conference.

[17]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.