Boolean satisfiability and equivalence checking using general binary decision diagrams
暂无分享,去创建一个
[1] Masahiro Fujita,et al. Evaluation and improvement of Boolean comparison method based on binary decision diagrams , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[2] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[3] Steven J. Friedman. Data structures for formal verification of circuit designs , 1990 .
[4] Randal E. Bryant,et al. On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication , 1991, IEEE Trans. Computers.
[5] Robert K. Brayton,et al. Implicit state enumeration of finite state machines using BDD's , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[6] C. L. Berman. Ordered binary decision diagrams and circuit structure , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[7] Jerry R. Burch,et al. Using bdds to verify multipliers , 1991, 28th ACM/IEEE Design Automation Conference.
[8] Srinivas Devadas. Comparing two-level and ordered binary decision diagram representations of logic functions , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] Albert R. Wang,et al. Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.