Boolean satisfiability and equivalence checking using general binary decision diagrams

It is shown how general binary decision diagrams (BDDs), i.e., BDDs where input variables are allowed to appear multiple times along any path in the BDD, can be used to check for Boolean satisfiability. This satisfiability checking strategy is based on an input smoothing operation on general BDDs. Various input smoothing strategies for general BDDs are developed. In order to verify the equivalence of two functions f/sub 1/ and f/sub 2/, f/sub 1/(+)f/sub 2/ is checked for satisfiability. Using general BDDs different implementations of a 16*16 multiplier, a modified Achilles' heel function and a complex add-shift function were verified. It was not possible to construct OBDDs for any of the three functions.<<ETX>>

[1]  Masahiro Fujita,et al.  Evaluation and improvement of Boolean comparison method based on binary decision diagrams , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[2]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[3]  Steven J. Friedman Data structures for formal verification of circuit designs , 1990 .

[4]  Randal E. Bryant,et al.  On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication , 1991, IEEE Trans. Computers.

[5]  Robert K. Brayton,et al.  Implicit state enumeration of finite state machines using BDD's , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[6]  C. L. Berman Ordered binary decision diagrams and circuit structure , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[7]  Jerry R. Burch,et al.  Using bdds to verify multipliers , 1991, 28th ACM/IEEE Design Automation Conference.

[8]  Srinivas Devadas Comparing two-level and ordered binary decision diagram representations of logic functions , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Albert R. Wang,et al.  Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.