A 1V 16.9ppm/°C 250nA Switched-Capacitor CMOS Voltage Reference

We have developed a switched-capacitor CMOS voltage reference (SCVR). The circuit is shown in Fig. 24.3.2 and is composed of a low-power bias circuit [G. De Vita and G. iannacone, 2007], a core circuit and a switched-capacitor difference amplifier that is insensitive to op-amp offset voltage. The clock signals (phi<sub>1</sub>, phi<sub>2</sub>, phi<sub>2</sub>') are non-overlapping to prevent leakage. The core circuit supplies V<sub>gs1</sub> and V<sub>gs2</sub> to the switched-capacitor difference amplifier on phases phi<sub>1</sub> and phi<sub>2</sub>, respectively. The difference amplifier then generates an output, which has a low TC, based on the gate-source voltage difference, AVGS.

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