A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

This paper proposes a novel 12-bit column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for high-speed CMOS image sensors. Cooperating with the output offset storage (OOS) technique, a new correlated double sampling (CDS) is adopted to reduce the non-uniformity in column-level ADCs. In the proposed structure, the decision point of the comparator is independent of the input signal. The variation of the comparator offset caused by the input level is eliminated. Through a foreground calibration, the non-idealities from the ramp generator and the column ADC are both corrected. Design and simulation in a 130nm CMOS process, the proposed ADC achieves the differential nonlinearity (DNL) of +0.76/−0.8 LSB and the integral nonlinearity (INL) of +1.06/−0.84 LSB at a sampling frequency of 100 KS/s with the calibration. The effective number of bits (ENOB) is also improved from 4.66 bits to 11.25 bits. The single ADC occupies an active area of <inline-formula> <tex-math notation="LaTeX">$7.5\times 775\,\,\mu \text{m}^{2}$ </tex-math></inline-formula> and the power consumption is <inline-formula> <tex-math notation="LaTeX">$72~\mu \text{W}$ </tex-math></inline-formula>.

[1]  Qihui Zhang,et al.  A High Area-Efficiency 14-bit SAR ADC With Hybrid Capacitor DAC for Array Sensors , 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Zhangming Zhu,et al.  A 9.1ENOB 200MS/s Asynchronous SAR ADC With Hybrid Single-Ended/Differential DAC in 55-nm CMOS for Image Sensing Signals , 2018, IEEE Sensors Journal.

[3]  Wan Kim,et al.  Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Jiangtao Xu,et al.  A 12-Bit High-Speed Column-Parallel Two-Step Single-Slope Analog-to-Digital Converter (ADC) for CMOS Image Sensors , 2014, Sensors.

[5]  Masanori Furuta,et al.  A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[6]  Kaiming Nie,et al.  A Single Slope ADC With Row-Wise Noise Reduction Technique for CMOS Image Sensor , 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Dongsoo Kim,et al.  A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs , 2009, IEEE Transactions on Electron Devices.

[8]  Oh-Kyong Kwon,et al.  A Small-Area and Energy-Efficient 12-bit SA-ADC With Residue Sampling and Digital Calibration for CMOS Image Sensors , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Oh-Kyong Kwon,et al.  10-bit Driver IC Using 3-bit DAC Embedded Operational Amplifier for Spatial Optical Modulators (SOMs) , 2007, IEEE Journal of Solid-State Circuits.

[10]  Jinwook Burm,et al.  High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  R. Jacob Baker.  Resistors, Capacitors, MOSFETs , 2011 .

[12]  Youngcheol Chae,et al.  A Two-Step A/D Conversion and Column Self-Calibration Technique for Low Noise CMOS Image Sensors , 2014, Sensors.

[13]  George Jie Yuan,et al.  Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering , 2012, IEEE Journal of Solid-State Circuits.

[14]  Atila Alvandpour,et al.  Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[15]  Daehyeok Kim,et al.  A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems , 2017, Sensors.

[16]  Wouter A. Serdijn,et al.  Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Behzad Razavi,et al.  Design techniques for high-speed, high-resolution comparators , 1992 .

[18]  Youngcheol Chae,et al.  A 640×640 Fully Dynamic CMOS Image Sensor for Always-On Object Recognition , 2019, 2019 Symposium on VLSI Circuits.

[19]  Tatsuya Ichikawa,et al.  A 17.7Mpixel 120fps CMOS image sensor with 34.8Gb/s readout , 2011, 2011 IEEE International Solid-State Circuits Conference.

[20]  A. Suzuki,et al.  High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[21]  Pedro M. Figueiredo,et al.  Kickback noise reduction techniques for CMOS latched comparators , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[22]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[23]  J. Burm,et al.  Low Power CMOS Image Sensors Using Two Step Single Slope ADC With Bandwidth-Limited Comparators & Voltage Range Extended Ramp Generator for Battery-Limited Application , 2020, IEEE Sensors Journal.

[24]  Shoji Kawahito,et al.  A 1.7-in, 33-Mpixel, 120-frames/s CMOS Image Sensor With Depletion-Mode MOS Capacitor-Based 14-b Two-Stage Cyclic A/D Converters , 2016, IEEE Transactions on Electron Devices.

[25]  M.F. Snoeij,et al.  Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors , 2007, IEEE Journal of Solid-State Circuits.

[26]  S. Watanabe,et al.  A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change , 2006, IEEE Journal of Solid-State Circuits.

[27]  Leif Lindgren.  A New Simultaneous Multislope ADC Architecture for Array Implementations , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[28]  Shoji Kawahito,et al.  A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC , 2012, IEEE Journal of Solid-State Circuits.

[29]  Oh-Kyong Kwon,et al.  A Low-Power CMOS Image Sensor With Area-Efficient 14-bit Two-Step SA ADCs Using Pseudomultiple Sampling Method , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[30]  Mau-Chung Frank Chang,et al.  A 10-bit Resistor-Floating-Resistor-String DAC (RFR-DAC) for High Color-Depth LCD Driver ICs , 2012, IEEE Journal of Solid-State Circuits.

[31]  Amine Bermak,et al.  Low-Power CMOS Image Sensor Based on Column-Parallel Single-Slope/SAR Quantization Scheme , 2013, IEEE Transactions on Electron Devices.