Fast Hardware-Software Co-simulation Using Software Synthesis and Estimation

In this paper we describe a technique for hardware-software co-simulation that is almost cycle-accurate, but does not require the use of interprocess communication nor a C language interface for the software components. Software is modeled by using behavioral VHDL constructs, annotated with timing information derived by basic block-level timing estimates. Execution of the VHDL processes modeling software tasks is coordinated by a process emulating the target RTOS behavior. The eeects of changing the HW/SW partition can be quickly estimated by changing a process parameter deening its target implementation and the processor on which it is running 5].