Case study on multiple fault dependability and security evaluations

The increasing level of integration and decreasing size of circuit elements leads to higher probabilities of operational faults. More vulnerable electronic devices are also more prone to external influence from energizing radiation. Additionally, the concerns of chip designers include not only the natural causes of faults but also the misbehavior of chips due to ''planned'' attacks, as, for example, in critical security applications. In particular, smart cards are exposed to complex attacks through which an adversary attempts to extract knowledge from secured systems by provoking undefined states. These problems increase the need to test new designs for their fault robustness. This paper presents a case study on fault injection strategies. An in-system fault injection strategy for automatic test pattern injection by enabling the emulation of fault effects on the circuit level is introduced. Second, an approach is presented that provides an abstraction of the internal fault injection structures to a more generic high-level view. Through this abstraction, it is possible to help the operating system designer test a product against different fault effects without knowing how to produce this effect by a fault attack. Therefore, we implemented a modular fault injection controller that is located along with the system under test on the emulator platform.

[1]  Massimo Violante,et al.  An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits , 2002, J. Electron. Test..

[2]  Charles E. Stroud,et al.  Embedded Processor Based Fault Injection and SEU Emulation for FPGAs , 2009, ESA.

[3]  Régis Leveugle,et al.  Using run-time reconfiguration for fault injection in hardware prototypes , 2000, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[4]  Marcus Jeitler,et al.  FuSE - a hardware accelerated HDL fault injection tool , 2009, 2009 5th Southern Conference on Programmable Logic (SPL).

[5]  Yves Crouzet,et al.  MEFISTO-L: a VHDL-based fault injection tool for the experimental assessment of fault tolerance , 1998, Digest of Papers. Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing (Cat. No.98CB36224).

[6]  Christian Steger,et al.  Automatic saboteur placement for emulation-based multi-bit fault injection , 2011, 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC).

[7]  Alfredo Benso,et al.  Fault Injection Techniques and Tools for Embedded Systems , 2003 .

[8]  David Naccache,et al.  The Sorcerer's Apprentice Guide to Fault Attacks , 2006, Proceedings of the IEEE.

[9]  C. Lopez-Ongil,et al.  A Unified Environment for Fault Injection at Any Design Level Based on Emulation , 2007, IEEE Transactions on Nuclear Science.

[10]  Régis Leveugle,et al.  Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments , 2003, J. Electron. Test..

[11]  Christian Steger,et al.  Modular Fault Injector for Multiple Fault Dependability and Security Evaluations , 2011, 2011 14th Euromicro Conference on Digital System Design.

[12]  Pedro J. Gil,et al.  Improvement of fault injection techniques based on VHDL code modification , 2005, Tenth IEEE International High-Level Design Validation and Test Workshop, 2005..

[13]  David de Andrés,et al.  FADES: a fault emulation tool for fast dependability assessment , 2006, 2006 IEEE International Conference on Field Programmable Technology.

[14]  Raimund Ubar,et al.  FPGA based fault emulation of synchronous sequential circuits , 2004, Proceedings Norchip Conference, 2004..

[15]  Christian Steger,et al.  Automated Power Characterization for Run-Time Power Emulation of SoC Designs , 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

[16]  Mario Porrmann,et al.  vMAGIC - Automatic Code Generation for VHDL , 2009, Int. J. Reconfigurable Comput..

[17]  R. Leveugle.  Early Analysis of Fault-based Attack Effects in Secure Circuits , 2007, IEEE Transactions on Computers.

[18]  Sara Blanc,et al.  Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Todd M. Austin,et al.  Fault-based attack of RSA authentication , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[20]  Michael Nicolaidis.  Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[21]  Eric Peeters,et al.  Memories: A Survey of Their Secure Uses in Smart Cards , 2003, Second IEEE International Security in Storage Workshop.

[22]  O. Novak,et al.  A Novel Emulation Technique that Preserves Circuit Structure and Timing , 2007, 2007 International Symposium on System-on-Chip.

[23]  Jean-Marc Daveau,et al.  An industrial fault injection platform for soft-error dependability analysis and hardening of complex system-on-a-chip , 2009, 2009 IEEE International Reliability Physics Symposium.

[24]  Leos Kafka.  Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs , 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

[25]  Todd M. Austin,et al.  CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework , 2008, 2008 IEEE International Conference on Computer Design.