A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

With the end of both Dennard’s scaling and Moore’s law, computer users and researchers are aggressively exploring alternative forms of computing in order to continue the performance scaling that we have come to enjoy. Among the more salient and practical of the post-Moore alternatives are reconfigurable systems, with Coarse-Grained Reconfigurable Architectures (CGRAs) seemingly capable of striking a balance between performance and programmability. In this paper, we survey the landscape of CGRAs. We summarize nearly three decades of literature on the subject, with a particular focus on the premise behind the different CGRAs and how they have evolved. Next, we compile metrics of available CGRAs and analyze their performance properties in order to understand and discover knowledge gaps and opportunities for future CGRA research specialized towards High-Performance Computing (HPC). We find that there are ample opportunities for future research on CGRAs, in particular with respect to size, functionality, support for parallel programming models, and to evaluate more complex applications.

[1]  Peter Jamieson,et al.  READY: A Fine-Grained Multithreading Overlay Framework for Modern CPU-FPGA Dataflow Applications , 2019, ACM Trans. Embed. Comput. Syst..

[2]  Luigi Carro,et al.  A reconfigurable heterogeneous multicore with a homogeneous ISA , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[3]  Kees A. Vissers,et al.  Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP) , 2019, FPGA.

[4]  Karthikeyan Sankaralingam,et al.  DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing , 2012, IEEE Micro.

[5]  Prashant Sharma,et al.  RiBoSOM: rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform , 2018, SAMOS.

[6]  Ronald G. Dreslinski,et al.  The M5 Simulator: Modeling Networked Systems , 2006, IEEE Micro.

[7]  Kiyoung Choi,et al.  FloRA: Coarse-grained reconfigurable architecture with floating-point operation capability , 2009, 2009 International Conference on Field-Programmable Technology.

[8]  Syed M. A. H. Jafri,et al.  The SiLago Solution: Architecture and Design Methods for a Heterogeneous Dark Silicon Aware Coarse Grain Reconfigurable Fabric , 2017 .

[9]  Jason Helge Anderson,et al.  CGRA-ME: A unified framework for CGRA modelling and exploration , 2017, 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

[10]  DengYangdong,et al.  A Survey of Coarse-Grained Reconfigurable Architecture and Design , 2019 .

[11]  Dan Mansur.  Stratix IV FPGA and HardCopy IV ASIC @ 40 nm , 2008, 2008 IEEE Hot Chips 20 Symposium (HCS).

[12]  Jean-Michel Chabloz,et al.  Globally-Ratiochronous, Locally-Synchronous Systems , 2012 .

[13]  Karthikeyan Sankaralingam,et al.  Dark Silicon and the End of Multicore Scaling , 2012, IEEE Micro.

[14]  Márcio Eduardo Kreutz,et al.  A Coarse-Grained Reconfigurable Architecture for a PRET Machine , 2018, 2018 VIII Brazilian Symposium on Computing Systems Engineering (SBESC).

[15]  Kiyoung Choi,et al.  Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures , 2008, Int. J. Embed. Syst..

[16]  Markus Weinhardt,et al.  A Coarse-Grained Reconfigurable Array for High-Performance Computing Applications , 2018, 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

[17]  Wenjie Wang,et al.  A reconfigurable multi-processor SoC for media applications , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[18]  Guido Baccelli.  Design of a Coarse Grain Reconfigurable Array for Neural Networks , 2019 .

[19]  Todd M. Austin,et al.  SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.

[20]  Tarek S. Abdelrahman,et al.  Towards Synthesis-Free JIT Compilation to Commodity FPGAs , 2011, 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines.

[21]  Carl Ebeling,et al.  RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.

[22]  Vaughn Betz,et al.  Comparing performance, productivity and scalability of the TILT overlay processor to OpenCL HLS , 2014, 2014 International Conference on Field-Programmable Technology (FPT).

[23]  Hideharu Amano,et al.  Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping , 2018, HEART.

[24]  Reiner W. Hartenstein,et al.  A reconfigurable data-driven ALU for Xputers , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[25]  Scott A. Mahlke,et al.  CGRA express: accelerating execution using dynamic operation fusion , 2009, CASES '09.

[26]  Satoshi Matsuoka,et al.  Designing and accelerating spiking neural networks using OpenCL for FPGAs , 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

[27]  William J. Dally,et al.  Evaluating the Imagine stream architecture , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[28]  Wayne Luk,et al.  Stream Processing Dual-Track CGRA for Object Inference , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[29]  Wei Cao,et al.  DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

[30]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[31]  Markus Weinhardt,et al.  PACT XPP—A Self-Reconfigurable Data Processing Architecture , 2003, The Journal of Supercomputing.

[32]  Henk Corporaal,et al.  Coarse grained reconfigurable architectures in the past 25 years: Overview and classification , 2016, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS).

[33]  Luigi Carro,et al.  Towards a Dynamic and Reconfigurable Multicore Heterogeneous System , 2014, 2014 Brazilian Symposium on Computing Systems Engineering.

[34]  José T. de Sousa,et al.  Versat, a Minimal Coarse-Grain Reconfigurable Array , 2016, VECPAR.

[35]  Davide Rossi,et al.  A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[36]  Douglas L. Maskell,et al.  DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect , 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[37]  Hideharu Amano,et al.  Variable pipeline structure for Coarse Grained Reconfigurable Array CMA , 2016, 2016 International Conference on Field-Programmable Technology (FPT).

[38]  Russell Tessier,et al.  c ○ 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. Reconfigurable Computing for Digital Signal Processing: A Survey ∗ , 1999 .

[39]  Tony Stansfield.  Using Multiplexers for Control and Data in D-Fabrix , 2003, FPL.

[40]  Michael Butler,et al.  Bulldozer: An Approach to Multithreaded Compute Performance , 2011, IEEE Micro.

[41]  Francisco Carlos Silva Junior,et al.  A Partially Shared Thin Reconfigurable Array For Multicore Processor , 2019 .

[42]  Kentaro Sano,et al.  A Template-based Framework for Exploring Coarse-Grained Reconfigurable Architectures , 2020, 2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP).

[43]  Hiroshi Nakamura,et al.  Cool Mega-Array: A highly energy efficient reconfigurable accelerator , 2011, 2011 International Conference on Field-Programmable Technology.

[44]  Seth Copen Goldstein,et al.  Tartan: evaluating spatial computation for whole program execution , 2006, ASPLOS XII.

[45]  Mario Konijnenburg,et al.  ULP-SRP: Ultra low power Samsung Reconfigurable Processor for biomedical applications , 2012, 2012 International Conference on Field-Programmable Technology.

[46]  Rudy Lauwereins,et al.  ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix , 2003, FPL.

[47]  William J. Dally,et al.  A bandwidth-efficient architecture for media processing , 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.

[48]  Hideharu Amano,et al.  Stream applications on the dynamically reconfigurable processor , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[49]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[50]  Jari Nurmi,et al.  A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities , 2008, Journal of Real-Time Image Processing.

[51]  J. Hoe,et al.  OpenSPARC : An Open Platform for Hardware Reliability Experimentation , 2008 .

[52]  David Kirk,et al.  NVIDIA cuda software and gpu parallel computing architecture , 2007, ISMM '07.

[53]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[54]  V. Baumgarte,et al.  PACT XPP-A Self-Reconfigurable Data Processing Architecture , 2001 .

[55]  Theingi Myint,et al.  A SLM-based overlay architecture for fine-grained virtual FPGA , 2019, IEICE Electron. Express.

[56]  Diogo Sousa,et al.  Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices , 2017, 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

[57]  Fadi J. Kurdahi,et al.  The MorphoSys Parallel Reconfigurable System , 1999, Euro-Par.

[58]  Jari Nurmi,et al.  CREMA: A coarse-grain reconfigurable array with mapping adaptiveness , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[59]  Bill Salefski,et al.  Re-configurable computing in wireless , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[60]  Henry Hoffmann,et al.  The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs , 2002, IEEE Micro.

[61]  A. Tsai,et al.  PipeRench: A virtualized programmable datapath in 0.18 micron technology , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[62]  Bruce Jacob,et al.  DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator , 2020, IEEE Computer Architecture Letters.

[63]  Frank Vahid,et al.  Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only) , 2005, FPGA '05.

[64]  Jaehyuk Huh,et al.  TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP , 2004, TACO.

[65]  André DeHon,et al.  MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[66]  Luca Benini,et al.  A 142MOPS/mW integrated programmable array accelerator for smart visual processing , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[67]  John L. Henning.  SPEC CPU2006 benchmark descriptions , 2006, CARN.

[68]  Guy Lemieux,et al.  ZUMA: An Open FPGA Overlay Architecture , 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

[69]  Alejandro Duran,et al.  Ompss: a Proposal for Programming Heterogeneous Multi-Core Architectures , 2011, Parallel Process. Lett..

[70]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[71]  Christian Hochberger,et al.  AMIDAR Project: Lessons Learned in 15 Years of Researching Adaptive Processors , 2018, 2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).

[72]  David M. Lewis,et al.  Architectural enhancements in Stratix V™ , 2013, FPGA '13.

[73]  Cheng Liu,et al.  Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay , 2015, ArXiv.

[74]  Karthikeyan Sankaralingam,et al.  Stream-dataflow acceleration , 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

[75]  Jason Cong,et al.  A Fully Pipelined and Dynamically Composable Architecture of CGRA , 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

[76]  Kunjan Patel,et al.  SYSCORE: A Coarse Grained Reconfigurable Array Architecture for Low Energy Biosignal Processing , 2011, 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines.

[77]  Georgi Gaydadjiev,et al.  Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array , 2007, ARC.

[78]  Reiner W. Hartenstein,et al.  A New FPGA Architecture for Word-Oriented Datapaths , 1994, FPL.

[79]  Guy Lemieux,et al.  Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor , 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[80]  Satoshi Matsuoka,et al.  Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL , 2018, FPGA.

[81]  Vivek Sarkar,et al.  Baring it all to Software: The Raw Machine , 1997 .

[82]  Vivienne Sze,et al.  Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices , 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[83]  Steven Swanson,et al.  The WaveScalar architecture , 2007, TOCS.

[84]  Stephen Dean Brown.  FPGA Architectural Research: A Survey , 1996, IEEE Des. Test Comput..

[85]  Kavitha T. Madhu,et al.  RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels , 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

[86]  Karthikeyan Sankaralingam,et al.  Design, integration and implementation of the DySER hardware accelerator into OpenSPARC , 2012, IEEE International Symposium on High-Performance Comp Architecture.

[87]  Scott A. Mahlke,et al.  Polymorphic Pipeline Array: A flexible multicore accelerator with virtualized execution for mobile multimedia applications , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[88]  Carl Ebeling,et al.  Mapping applications to the RaPiD configurable architecture , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[89]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.

[90]  Jason Helge Anderson,et al.  Generic Connectivity-Based CGRA Mapping via Integer Linear Programming , 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[91]  Liang Yang,et al.  Design and evaluation of a novel reconfigurable ALU based on FPGA , 2013, Proceedings 2013 International Conference on Mechatronic Sciences, Electric Engineering and Computer (MEC).

[92]  Dirk Koch,et al.  Partial Reconfiguration on FPGAs - Architectures, Tools and Applications , 2012, Lecture Notes in Electrical Engineering.

[93]  Aaron Smith,et al.  Compiling for EDGE architectures , 2006, International Symposium on Code Generation and Optimization (CGO'06).

[94]  Martin Langhammer,et al.  Floating-Point DSP Block Architecture for FPGAs , 2015, FPGA.

[95]  Satoshi Matsuoka,et al.  Evaluating and Optimizing OpenCL Kernels for High Performance Computing with FPGAs , 2016, SC16: International Conference for High Performance Computing, Networking, Storage and Analysis.

[96]  Luca Benini,et al.  A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[97]  Abdullah Atalar,et al.  BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[98]  Doug Burger,et al.  The design and implementation of the TRIPS prototype chip , 2005, 2005 IEEE Hot Chips XVII Symposium (HCS).

[99]  Shorin Kyo,et al.  IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements , 2001, Proceedings 2001 International Conference on Image Processing (Cat. No.01CH37205).

[100]  Andreas Moshovos,et al.  CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit , 2000, ISCA '00.

[101]  David Atienza,et al.  i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing , 2019, IEEE Embedded Systems Letters.

[102]  Jari Nurmi,et al.  Effects of scaling a coarse-grain reconfigurable array on power and energy consumption , 2012, 2012 International Symposium on System on Chip (SoC).

[103]  William J. Dally,et al.  SCNN: An accelerator for compressed-sparse convolutional neural networks , 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

[104]  Russell Tessier,et al.  FPGA Architecture: Survey and Challenges , 2008, Found. Trends Electron. Des. Autom..

[105]  Sagheer Ahmad,et al.  Xilinx First 7nm Device: Versal AI Core (VC1902) , 2019, 2019 IEEE Hot Chips 31 Symposium (HCS).

[106]  Karthikeyan Sankaralingam,et al.  Routed inter-ALU networks for ILP scalability and performance , 2003, Proceedings 21st International Conference on Computer Design.

[107]  Hong Wang,et al.  Intel® atom™ processor core made FPGA-synthesizable , 2009, FPGA '09.

[108]  Guy Lemieux,et al.  Rapid Overlay Builder for Xilinx FPGAs , 2015, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines.

[109]  Rohit Chandra,et al.  Parallel programming in openMP , 2000 .

[110]  Kunle Olukotun,et al.  REMARC : Reconfigurable Multimedia Array Coprocessor , 1999 .

[111]  Jürgen Becker,et al.  Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures , 2000, PDPTA.

[112]  Martin Margala,et al.  MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor , 2009, 2009 NASA/ESA Conference on Adaptive Hardware and Systems.

[113]  Kiyoung Choi,et al.  Chip implementation of a coarse-grained reconfigurable architecture supporting floating-point operations , 2008, 2008 International SoC Design Conference.

[114]  David Atienza,et al.  A multi-core reconfigurable architecture for ultra-low power bio-signal analysis , 2016, 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS).

[115]  Chirag Ravishankar,et al.  Xilinx Adaptive Compute Acceleration Platform: VersalTM Architecture , 2019, FPGA.

[116]  Tarek S. Abdelrahman,et al.  A high-performance overlay architecture for pipelined execution of data flow graphs , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[117]  Henry Hoffmann,et al.  Evaluation of the Raw microprocessor: an exposed-wire-delay architecture for ILP and streams , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[118]  Neil W. Bergmann,et al.  QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks , 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

[119]  Neil W. Bergmann,et al.  QUKU: A dual-layer reconfigurable architecture , 2013, ACM Trans. Embed. Comput. Syst..

[120]  Jean Vuillemin,et al.  A reconfigurable arithmetic array for multimedia applications , 1999, FPGA '99.

[121]  Fan Feng,et al.  Floating-point operation based reconfigurable architecture for radar processing , 2016, IEICE Electron. Express.

[122]  Reiner W. Hartenstein,et al.  Using the KressArray for reconfigurable computing , 1998, Other Conferences.

[123]  R. Kisiel,et al.  Trends in assembling of advanced IC packages , 2005 .

[124]  Karthikeyan Sankaralingam,et al.  Software Infrastructure and Tools for the TRIPS Prototype , 2007 .

[125]  Muhammad Shafique,et al.  X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[126]  Zeyad Tariq Aklah,et al.  A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly of Custom Accelerators on FPGAs , 2017 .

[127]  S. Kumar,et al.  A benchmark suite for evaluating configurable computing systems—status, reflections, and future directions , 2000, FPGA '00.

[128]  M. Oskin,et al.  The Microarchitecture of a Pipelined WaveScalar Processor : An RTL-based Study , 2005 .

[129]  Paolo Bonzini,et al.  EGRA: A Coarse Grained Reconfigurable Architectural Template , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[130]  Yoav Etsion,et al.  Single-graph multiple flows: Energy efficient design alternative for GPGPUs , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

[131]  Karthikeyan Sankaralingam,et al.  Exploring the potential of heterogeneous Von Neumann/dataflow execution models , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

[132]  Luca Benini,et al.  TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE , 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[133]  James Ball.  The nios II family of configurable soft-core processors , 2005, 2005 IEEE Hot Chips XVII Symposium (HCS).

[134]  Jian Weng,et al.  Towards General Purpose Acceleration by Exploiting Common Data-Dependence Forms , 2019, MICRO.

[135]  Guigang Zhang,et al.  Deep Learning , 2016, Int. J. Semantic Comput..

[136]  Wu-chun Feng,et al.  The Green500 List: Encouraging Sustainable Supercomputing , 2007, Computer.

[137]  David Wentzlaff,et al.  Processor: A 64-Core SoC with Mesh Interconnect , 2010 .

[138]  Joseph R. Cavallaro,et al.  FPGA prototyping of a high data rate LTE uplink baseband receiver , 2009, 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers.

[139]  Hideharu Amano,et al.  A Survey on Dynamically Reconfigurable Processors , 2006, IEICE Trans. Commun..

[140]  Rudy Lauwereins,et al.  DRESC: a retargetable compiler for coarse-grained reconfigurable architectures , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[141]  Wafer-Scale Deep Learning , 2019, 2019 IEEE Hot Chips 31 Symposium (HCS).

[142]  Martin Margala,et al.  A C++-embedded Domain-Specific Language for programming the MORA soft processor array , 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

[143]  Cao Liang,et al.  SmartCell: An Energy Efficient Coarse-Grained Reconfigurable Architecture for Stream-Based Applications , 2009, EURASIP J. Embed. Syst..

[144]  Norbert Wehn,et al.  eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex , 2019, Journal of Signal Processing Systems.

[145]  John Wawrzynek,et al.  The Garp Architecture and C Compiler , 2000, Computer.

[146]  Valavan Manohararajah,et al.  The Stratix™ 10 Highly Pipelined FPGA Architecture , 2016, FPGA.

[147]  Rudy Lauwereins,et al.  Architecture exploration for a reconfigurable architecture template , 2005, IEEE Design & Test of Computers.

[148]  Amin Ansari,et al.  Bundled execution of recurring traces for energy-efficient general purpose processing , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[149]  Zhiyi Yu,et al.  A 167-Processor Computational Platform in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[150]  Mladen Berekovic,et al.  MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture , 2007, ARC.

[151]  Zheng Wang,et al.  A CGRA based Neural Network Inference Engine for Deep Reinforcement Learning , 2018, 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

[152]  James Coole,et al.  Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation , 2011, IEEE Embedded Systems Letters.

[153]  Aaron Smith,et al.  Towards an Area-Efficient Implementation of a High ILP EDGE Soft Processor , 2018, ArXiv.

[154]  Scott A. Mahlke,et al.  VEAL: Virtualized Execution Accelerator for Loops , 2008, 2008 International Symposium on Computer Architecture.

[155]  Shorin Kyo,et al.  IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements , 2011, J. Signal Process. Syst..

[156]  Ahmed Hemani.  Dynamically Reconfigurable Resource Array , 2008 .

[157]  Thomas N. Theis,et al.  The End of Moore's Law: A New Beginning for Information Technology , 2017, Computing in Science & Engineering.

[158]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[159]  Luigi Carro,et al.  An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture , 2011, 2011 Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES).

[160]  Kavitha T. Madhu,et al.  Compiling HPC Kernels for the REDEFINE CGRA , 2015, 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems.

[161]  Vaishali Tehre,et al.  Survey on Coarse Grained Reconfigurable Architectures , 2012 .

[162]  Jeffrey R. Diamond,et al.  An evaluation of the TRIPS computer system , 2009, ASPLOS.

[163]  Douglas L. Maskell,et al.  Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq , 2016, SIGARCH Comput. Archit. News.

[164]  Catherine D. Schuman,et al.  Neuromorphic Computing : A Post-Moore ’ s Law Complementary Architecture , 2016 .

[165]  Woody Sherman,et al.  Molecular Dynamics Range-Limited Force Evaluation Optimized for FPGAs , 2019, 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

[166]  Kenneth A. Ross,et al.  Q100: the architecture and design of a database processing unit , 2014, ASPLOS.

[167]  Emmett Kilgariff,et al.  Fermi GF100 GPU Architecture , 2011, IEEE Micro.

[168]  Neil W. Bergmann,et al.  QUKU: a two-level reconfigurable architecture , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[169]  Kunle Olukotun,et al.  Plasticine: A reconfigurable architecture for parallel patterns , 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

[170]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[171]  Cheng Liu,et al.  QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay , 2015, 2015 International Conference on Field Programmable Technology (FPT).

[172]  Kunle Olukotun,et al.  Spatial: a language and compiler for application accelerators , 2018, PLDI.

[173]  Erik Lindholm,et al.  NVIDIA Tesla: A Unified Graphics and Computing Architecture , 2008, IEEE Micro.

[174]  Yoav Etsion,et al.  Inter-Thread Communication in Multithreaded, Reconfigurable Coarse-Grain Arrays , 2018, 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[175]  Jan Gray.  GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator , 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[176]  Kolin Paul,et al.  reMORPH: A Runtime Reconfigurable Architecture , 2012, 2012 15th Euromicro Conference on Digital System Design.

[177]  Jeffrey S. Vetter,et al.  Architectures for the Post-Moore Era , 2017, IEEE Micro.

[178]  Tomoyoshi Sato.  DAPDNA-2 a dynamically reconfigurable processor with 376 32-bit processing elements , 2005, 2005 IEEE Hot Chips XVII Symposium (HCS).

[179]  George Theodoridis,et al.  A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools , 2007 .

[180]  J. Gregory Steffan,et al.  TILT: A multithreaded VLIW soft processor family , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[181]  Vivek Sarkar,et al.  The Raw Compiler Project , 1999 .

[182]  Aaftab Munshi,et al.  The OpenCL specification , 2009, 2009 IEEE Hot Chips 21 Symposium (HCS).

[183]  Jari Nurmi,et al.  Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems , 2012, J. Signal Process. Syst..

[184]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[185]  Kunle Olukotun,et al.  A quantitative analysis of reconfigurable coprocessors for multimedia applications , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[186]  Tulika Mitra,et al.  HyCUBE: A CGRA with reconfigurable single-cycle multi-hop interconnect , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[187]  Yvon Savaria,et al.  Two-level configuration for FPGA: A new design methodology based on a computing fabric , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[188]  John H. Wuorinen.  1993 IEEE International Solid-State Circuits Conference : digest of technical papers , 1993 .

[189]  Lizy Kurian John,et al.  Scaling to the end of silicon with EDGE architectures , 2004, Computer.

[190]  Satoshi Matsuoka,et al.  Evaluating high-level design strategies on FPGAs for high-performance computing , 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

[191]  Yoshua Bengio,et al.  Training deep neural networks with low precision multiplications , 2014 .

[192]  Joel Emer,et al.  Eyeriss: an Energy-efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks Accessed Terms of Use , 2022 .

[193]  Yunheung Paek,et al.  Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture , 2012, ARC.

[194]  Norman P. Jouppi,et al.  MIPS: A microprocessor architecture , 1982, MICRO 15.