A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme
暂无分享,去创建一个
[1] Michael P. Flynn,et al. A 22Gb/s, 10mm on-chip serial link over lossy transmission line with resistive termination , 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).
[2] Yehea I. Ismail,et al. A 12Gbps all digital low power SerDes transceiver for on-chip networking , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).
[3] R. H. Havemann,et al. High-performance interconnects: an integration overview , 2001, Proc. IEEE.
[4] Yehea I. Ismail,et al. A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).
[5] Yehea I. Ismail,et al. Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).