Non-Robust versus Robust

[1]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[2]  Kaushik Roy,et al.  Synthesis of delay fault testable combinational logic , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[3]  John A. Waicukauski,et al.  On computing the sizes of detected delay faults , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Kurt Keutzer,et al.  Synthesis of robust delay-fault-testable circuits: practice , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  André Ivanov,et al.  Accelerated path delay fault simulation , 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

[6]  Vishwani D. Agrawal,et al.  Energy minimization based delay testing , 1992, [1992] Proceedings The European Conference on Design Automation.

[7]  Jacob Savir,et al.  Skewed-Load Transition Test: Part I, Calculus , 1992, Proceedings International Test Conference 1992.

[8]  Kurt Keutzer,et al.  Synthesis of robust delay-fault-testable circuits: theory , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Srinivas Patil,et al.  Skewed-Load Transition Test: Part II, Coverage , 1992, Proceedings International Test Conference 1992.

[10]  Kwang-Ting Cheng,et al.  Delay testing for non-robust untestable circuits , 1993, Proceedings of IEEE International Test Conference - (ITC).

[11]  Edward J. McCluskey,et al.  Three-pattern tests for delay faults , 1994, Proceedings of IEEE VLSI Test Symposium.