A Novel Program Scheme for Program Disturbance Optimization in 3-D NAND Flash Memory

A new program scheme using an “erase-like” waveform for precharge operation is proposed for program disturbance optimization in 3-D vertical channel flash memories. With the proposed scheme, the effect of precharge operation, which is followed by program operation, on the initial unselected channel is enhanced by charging additional holes from p-type well. Consequently, boosting efficiency and boosting potential of unselected string are promoted, leading to a significant suppressed program disturbance, and the ${V}_{\textsf {pass}}$ window can be enlarged notably as well. Meanwhile, the timing requirement of the proposed scheme is evaluated. The advantage of the erase assisted precharge scheme has been demonstrated by TCAD simulation and measurement in mini-array test-key device.

[1]  Jeong-Hyuk Choi,et al.  A New Cell-Type String Select Transistor in NAND Flash Memories for under 20nm Node , 2012, 2012 4th IEEE International Memory Workshop.

[2]  Ki-Hong Lee,et al.  Inherent Issues and Challenges of Program Disturbance of 3D NAND Flash Cell , 2012, 2012 4th IEEE International Memory Workshop.

[3]  SungJoo Hong,et al.  Modeling and optimization of the chip level program disturbance of 3D NAND Flash memory , 2013, 2013 5th IEEE International Memory Workshop.

[4]  Jungdal Choi,et al.  Effects of floating-gate interference on NAND flash memory cell operation , 2002 .

[5]  Mingxiang Wang,et al.  Separation of the Geometric Current in Charge Pumping Measurement of Polycrystalline Si Thin-Film Transistors , 2014, IEEE Transactions on Electron Devices.

[6]  Shinsugita-cho Isogo-ku,et al.  Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory , 2007 .

[7]  Sang-Ho Lee,et al.  Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation , 2016, IEEE Transactions on Electron Devices.

[8]  Chen-Hao Huang,et al.  A New Programming Scheme for the Improvement of Program Disturb Characteristics in Scaled nand Flash Memory , 2012, IEEE Transactions on Electron Devices.

[9]  Byung-Gook Park,et al.  New program inhibition scheme for high boosting efficiency in three-dimensional NAND array , 2014 .

[10]  Y. Iwata,et al.  Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory , 2007, 2007 IEEE International Electron Devices Meeting.

[11]  Chilhee Chung,et al.  Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure , 2010, 2010 Symposium on VLSI Technology.

[12]  Chih-Yuan Lu,et al.  Polycrystalline-silicon channel trap induced transient read instability in a 3D NAND flash cell string , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[13]  Xingqi Zou,et al.  A Novel Read Scheme for Read Disturbance Suppression in 3D NAND Flash Memory , 2017, IEEE Electron Device Letters.

[14]  Xingqi Zou,et al.  Leakage Characterization of Top Select Transistor for Program Disturbance Optimization in 3D NAND Flash , 2017 .

[15]  Jin Jang,et al.  Temperature dependent leakage currents in polycrystalline silicon thin film transistors , 1997 .

[16]  Chilhee Chung,et al.  New scaling limitation of the floating gate cell in NAND Flash Memory , 2010, 2010 IEEE International Reliability Physics Symposium.