A Wide-Band Low Power BiCMOS PLL

With the development and improvements of semiconductor process and technology, low‐cost consumer applications for radar transceiver systems have been proposed, such as automotive collision avoidance, cruise control, and fluid‐level indicators. High performance local oscillator (LO) signals with clean spectrum are required to down‐convert the received radio-frequency (RF) signal and up-convert the low frequency base-band signal to RF signal for radar transceivers. Phase-locked loop (PLL) is such a system that can be used to generate LO signals with large frequency range by tuning the integer or fractional divider. This chapter presents an integer-N PLL system comprised of a wide‐band VCO, divide‐by‐two circuit (DTC), multi‐modulus divider (MMD), phase-frequency detector (PFD) and charge pump (CP) in current-mode logic (CML) type, and divider modules for mixers and direct digital synthesis (DDS) clock.