SPICE-compatible thermal simulation with lumped circuit modeling for thermal reliability analysis based on modeling order reduction

With the growing power dissipation in modem high performance VLSI designs, nonuniform temperature distribution and limited heat-conduction capability have caused thermal induced performance and reliability degradation. However the problem modeled by finite difference method for interconnect reliability analysis has huge size if we require the resolution with wire width. In addition, the generated lumped circuit has significant number of input sources, and the bottleneck of traditional model reduction methods is the big number of input ports. In this paper we propose a method of SPICE-compatible thermal simulation for interconnect reliability analysis. The lumped thermal circuit modeling with adaptive approach is used to reduce the problem size. The improved extended Krylov subspace (IEKS) method, independent of the number of input ports, is used for thermal simulation. The experimental results show that our method provides highly accurate results with performance improvement 15 x over T-Spice for the problem with node number 72428.

[1]  Alberto L. Sangiovanni-Vincentelli,et al.  On thermal effects in deep sub-micron VLSI interconnects , 1999, DAC '99.

[2]  H. Pape,et al.  Thermal management of packaged IC by experimentally verified finite element modeling , 1997, Proceedings of the 1997 1st Electronic Packaging Technology Conference (Cat. No.97TH8307).

[3]  Robert W. Dutton,et al.  Full chip thermal simulation , 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

[4]  M. N. Özişik.  Boundary value problems of heat conduction , 1989 .

[5]  Robert W. Dutton,et al.  Fast placement-dependent full chip thermal simulation , 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

[6]  Janet Roveda,et al.  Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources , 2000, Proceedings 37th Design Automation Conference.

[7]  Kaustav Banerjee,et al.  Analysis of IR-drop scaling with implications for deep submicron P/G network designs , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[8]  Charlie Chung-Ping Chen,et al.  3-D Thermal-ADI: a linear-time chip level transient thermal simulator , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Sung-Mo Kang,et al.  ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  K. Banerjee,et al.  Global (interconnect) warming , 2001 .

[11]  Sung-Mo Kang,et al.  Interconnect thermal modeling for accurate simulation of circuittiming and reliability , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  G. B. Kromann.  Thermal management of a C4/ceramic-ball-grid array: the Motorola PowerPC 603/sup TM/ and PowerPC 604/sup TM/ RISC microprocessors , 1996, Twelfth Annual IEEE Semiconductor Thermal Measurement and Management Symposium. Proceedings.

[13]  Sung-Mo Kang,et al.  Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction , 2000, DAC.

[14]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.

[15]  Charlie Chung-Ping Chen,et al.  Thermal-ADI - a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Sung-Mo Kang,et al.  iTEM: a temperature-dependent electromigration reliability diagnosis tool , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..