VLSI design and implementation of adaptive channel equalizer

Signal integrity is critical to achieve reliable data communications. In non-ideal communication channels, signal quality deteriorates if the transmission rate and distance is pushed to the limit of the channel. Furthermore, in wireless channel, the effect of multipath propagation causes the transmitted signal to be superimposed, attenuated, and delayed at the receiver, which further deteriorates the signal. The problem, which is termed Intersymbol Interference (ISI), is overcome using channel equalizers. In addition to this, channel characteristics also vary with time, which requires the equalizer to adapt to the channel. This work presents the design of adaptive equalizer as applied in wireless systems as to achieve error proof data communication. The adaptive equalizer is designed using VHDL, and synthesized to TSMC 0.25 mum process technology with a proposed circuit architecture based on the least mean square (LMS) adaptive algorithm and linear FIR filter structure. From results obtained, the VLSI adaptive equalizer can successfully equalize distorted signals with ISI. Maximum throughput of 223 Kb/s and core cell area of 0.562 mm2 is achieved, which is suitable for mobile communication applications.

[1]  Leandro Soares Indrusiak,et al.  An efficient hardware implementation of a self-adaptable equalizer for WCDMA downlink UMTS standard , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[2]  M. Ishikawa,et al.  An adaptive line equalizer VLSI using digital signal processing , 1988 .

[3]  Markku Renfors,et al.  DSP implementation of low-complexity equalizer for multicarrier systems , 2003, Seventh International Symposium on Signal Processing and Its Applications, 2003. Proceedings..

[4]  Alberto Bellini,et al.  Design of a DSP-based 24 bit digital audio equalizer for automotive applications , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[5]  B. Daneshrad Signal processing ASIC requirements for high-speed wireless data communications , 1998, Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284).