Study of BiCMOS cache memory

To improve the speed of the processors for CPU of minicomputers and other systems, it is required to improve the machine cycle and the memory cycle, which are the performance indexes of the system. The general idea to realize a high-speed memory cycle is to apply the cache memory, which provides a hierarchical structure for the memory. This paper considers the realization of the cache memory by Hi-BiCMOS (high-performance bipolar CMOS) technology, which aims at a high-speed, highly integrated LSI by combining the microstructured CMOS and high-speed bipolar devices at the element level of the circuits. As the basic circuit, a RAM-combined Hi-BiCMOS circuit comparator is proposed, where the comparator logic is introduced into the sense amplifier of RAM. Applying the proposed circuit, TLB (Translation Lookaside Buffer) is designed and constructed, which performs the address transformation by cache memory. A satisfactory operation of the circuit was verified with the address conversion time of 13.3 ns. An evaluation by simulation was made for applying the proposed circuit to a 4K Byte cache memory, and it is indicated that the cache access through an address conversion can be made in 17.5 ns.