A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference preamplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18mum 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral nonlinearities of the prototype ADC are within 1.00LSB and 1.25LSB, respectively. The dual-channel ADC has an active area of 4.0mm2 and consumes 594mW at 1GS/s and 1.8V

[1]  Seung-Hoon Lee,et al.  An 11b 70 MHz 1.2 mm 2 49mW 0.18 um CMOS ADC with on–chip current/voltage references , 2002 .

[2]  S. Tsukamoto,et al.  A CMOS 6b 400 M sample/s ADC with error correction , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[3]  Xicheng Jiang,et al.  A 2GS/s 6b ADC in 0.18μm CMOS , 2003 .

[4]  M.-C.F. Chang,et al.  A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging , 2005, IEEE Journal of Solid-State Circuits.

[5]  Seung-Hoon Lee,et al.  An 11b 70-MHz 1.2-mm/sup 2/ 49-mW 0.18-/spl mu/m CMOS ADC with on-chip current/voltage references , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Shen-Iuan Liu,et al.  New dynamic flip-flops for high-speed dual-modulus prescaler , 1998, IEEE J. Solid State Circuits.