Limitations on MLC Flash Page Reuse and its Effects on Durability

Flash memory is prevalent in modern servers and devices. Coupled with the scaling down of flash technology, the popularity of flash memory motivates the search for methods to increase flash reliability and lifetime. Erasures are the dominant cause of flash cell wear, but reducing them is challenging because flash is a write-once medium— memory cells must be erased prior to writing. An approach that has recently received considerable attention relies onwrite-once memory (WOM) codes, designed to accommodate additional writes on write-once media. However, most techniques proposed for reusing flash pages with WOM codes are limited to SLC flash, and are not applicable to MLC flash due to the specific constraints it imposes. In this study, we use a hardware evaluation platform to identify the limitations of reprogramming flash pages on state-of-the-art MLC flash chips, and to directly measure the short and long-term effects of page reuse on SSD durability and energy consumption. Our findings provide key guidelines for FTL designs that employ WOM codes for reusing flash pages.

[1]  Jongmoo Choi,et al.  Caching less for better performance: balancing cache size and update cost of flash memory cache in hybrid storage systems , 2012, FAST.

[2]  Dan Feng,et al.  Improving flash-based disk cache with Lazy Adaptive Replacement , 2013, 2013 IEEE 29th Symposium on Mass Storage Systems and Technologies (MSST).

[3]  Hyojun Kim,et al.  BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage , 2008, FAST.

[4]  Amir Shpilka,et al.  Capacity-Achieving Multiwrite WOM Codes , 2012, IEEE Transactions on Information Theory.

[5]  Adi Shamir,et al.  How to Reuse a "Write-Once" Memory , 1982, Inf. Control..

[6]  Nanning Zheng,et al.  LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives , 2013, FAST.

[7]  Gérard D. Cohen,et al.  Linear binary code for write-once memories , 1986, IEEE Trans. Inf. Theory.

[8]  Anand Sivasubramaniam,et al.  Leveraging Value Locality in Optimizing NAND Flash-based SSDs , 2011, FAST.

[9]  Yuval Cassuto,et al.  NAND flash architectures reducing write amplification through multi-write codes , 2014, 2014 30th Symposium on Mass Storage Systems and Technologies (MSST).

[10]  Onur Mutlu,et al.  Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation , 2013, ICCD.

[11]  Wook-Ghee Hahn,et al.  7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[12]  Rina Panigrahy,et al.  Design Tradeoffs for SSD Performance , 2008, USENIX ATC.

[13]  David Burshtein,et al.  Polar Write Once Memory Codes , 2013, IEEE Trans. Inf. Theory.

[14]  Yue Wang,et al.  Exploiting Half-Wits: Smarter Storage for Low-Power Devices , 2011, FAST.

[15]  Xavier Jimenez,et al.  Wear unleveling: improving NAND flash lifetime by balancing page endurance , 2014, FAST.

[16]  Mircea R. Stan,et al.  Modeling Power Consumption of NAND Flash Memories Using FlashPower , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Improving MLC flash performance and endurance with extended P/E cycles , 2015, 2015 31st Symposium on Mass Storage Systems and Technologies (MSST).

[18]  Ethan L. Miller,et al.  Purity: Building Fast, Highly-Available Enterprise Flash Storage from Commodity Components , 2015, SIGMOD Conference.

[19]  David Burshtein,et al.  Polar write once memory codes , 2012, 2012 IEEE International Symposium on Information Theory Proceedings.

[20]  Dongkun Shin,et al.  ComboFTL: Improving performance and lifespan of MLC flash memory using SLC flash buffer , 2010, J. Syst. Archit..

[21]  Michael M. Swift,et al.  FlashTier: a lightweight, consistent and durable storage cache , 2012, EuroSys '12.

[22]  Wentao Huang,et al.  Rewriting flash memories by message passing , 2015, 2015 IEEE International Symposium on Information Theory (ISIT).

[23]  Paul H. Siegel,et al.  Characterizing flash memory: Anomalies, observations, and applications , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[24]  Trevor N. Mudge,et al.  Improving NAND Flash Based Disk Caches , 2008, 2008 International Symposium on Computer Architecture.

[25]  Fabio Margaglia,et al.  Extending SSD lifetime in database applications with page overwrites , 2013, SYSTOR '13.

[26]  Eitan Yaakobi,et al.  The Devil Is in the Details: Implementing Flash Page Reuse with WOM Codes , 2016, FAST.

[27]  Paul H. Siegel,et al.  Characterization and error-correcting codes for TLC flash memories , 2012, 2012 International Conference on Computing, Networking and Communications (ICNC).

[28]  Luis A. Lastras,et al.  Write amplification reduction in NAND Flash through multi-write coding , 2010, 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST).

[29]  Mahesh Balakrishnan,et al.  Extending SSD Lifetimes with Disk-Based Write Caches , 2010, FAST.

[30]  J. Kessenich,et al.  Bit error rate in NAND Flash memories , 2008, 2008 IEEE International Reliability Physics Symposium.

[31]  Nisha Talagala,et al.  HEC: improving endurance of high performance flash-based cache devices , 2013, SYSTOR '13.

[32]  Eitan Yaakobi,et al.  Write Once, Get 50% Free: Saving SSD Erase Costs Using WOM Codes , 2015, FAST.

[33]  Yeong-Taek Lee,et al.  A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories , 2008, IEEE Journal of Solid-State Circuits.

[34]  Paul H. Siegel,et al.  Codes for Write-Once Memories , 2012, IEEE Transactions on Information Theory.

[35]  Jongmoo Choi,et al.  Incremental redundancy to reduce data retention errors in flash-based SSDs , 2015, 2015 31st Symposium on Mass Storage Systems and Technologies (MSST).

[36]  David Burshtein Coding for asymmetric side information channels with applications to polar codes , 2015, 2015 IEEE International Symposium on Information Theory (ISIT).