Simple and accurate propagation delay model for submicron CMOS gates based on charge analysis

A simple method to evaluate the propagation delay of complex CMOS gates computed from inverter delay models based on the nth-power law MOSFET model is presented. The method is based on a transistor collapsing technique developed for complex gates and takes into account short-channel effects, internal coupling capacitances and the body effect. The propagation delay of complex gates for a 0.18 /spl mu/m technology is evaluated, showing excellent results.