On-Chip Optical Interconnects For Chip Multiprocessors

In this dissertation, we address the on-chip cross-core and-memory intercon-nection problem facing future large-scale chip multiprocessors (CMPs) through the use of silicon optical technology. CMOS-compatible silicon photonics is a disruptive technology that can potentially enable high-bandwidth, low-latency, and low-power interconnect solutions for both off-and on-chip data communication. Although the technology is still in its formative stages, and the more near-term application is chip-to-chip communication, rapid advances have been made in the development of on-chip optical interconnects and devices. We first investigate the potential of optical technology to construct a low-latency, high-bandwidth shared bus supporting snoopy cache coherence in future CMPs. While not exhaustive, our initial investigation yields a hierarchical opto-electrical system that exploits the advantages of optical technology while abiding by projected limitations. Our evaluation shows that, compared to an aggressive all-electrical bus of similar power and area, significant performance improvements can be achieved using an opto-electrical bus. This performance improvement is largely dependent on the number of implemented wavelengths per waveguide. We further improve on the data network. We present an all-optical approach to constructing data networks on chip that combines the following key features: (1) Wavelength-based routing, where the route followed by a packet depends solely on the wavelength of its carrier signal, and not on information either contained in the packet or traveling along with it. (2) Oblivious routing, by which the wavelength (and thus the route) employed to connect a source-destination pair is invariant for that pair, and does not depend on ongoing transmissions by other nodes, thereby simplifying design and operation. And (3) passive optical wavelength routers, whose routing pattern is set at design time, which allows for area and power optimizations not generally available to solutions that use dynamic routing. We construct such an all-optical network and propose a connection-based operation. Our evaluation shows that our approach is competitive with prior proposals from the performance standpoint, yet it yields significantly more power-efficient designs. on-chip optical interconnects for chip multiprocessors, she did research in areas of checkpointed processor architectures, reconfigurable processor architectures, and memory system design for chip multiprocessors. iii To my beloved family iv ACKNOWLEDGEMENTS First, I would like to sincerely thank Prof. José F. Martínez, my adviser, for continuously providing us with very crucial and effective feedback that have brought dramatical improvements, a lot of insights, and different perspectives to our research projects, writings, and presentations. His guidance, help, inspiration , and dedication …