A topology optimization method for low-power logic circuits with dual-threshold independent-gate FinFETs

This paper proposes a topology optimization method for dual-threshold (DT) independent-gate (IG) FinFET circuits. In the proposed method, a node extraction algorithm is developed to extract the characteristic nodes of a BDD expression, which are suitable to be realized with the compact logic gates based on the DT IG FinFET devices, and then the equivalent replacement program that these extracted characteristic parts are replaced with the compact logic gates is carried to obtain the final optimized circuit netlists. The MCNC benchmarks are used to verify the effectiveness of the proposed topology optimization method. All the circuits synthesized by the proposed method and the commercial synthesis tool (Design Compiler) are simulated using Hspice with FinFET BSIM model to fairly compare their circuit performances. The results show that the proposed method could greatly improve the performance of the circuits in terms of power dissipation and power delay product compared with the Design Compiler.

[1]  Niraj K. Jha,et al.  FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage , 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

[2]  Anish Muttreja,et al.  FinFET Circuit Design , 2011 .

[3]  Anamaria Martins Moreira,et al.  Advances in BDD reduction using Parallel Genetic Algorithms , 2001 .

[4]  Zhiyu Liu,et al.  Independent-gate and tied-gate FinFET SRAM Circuits: Design guidelines for reduced area and enhanced stability , 2007, 2007 Internatonal Conference on Microelectronics.

[5]  Kaushik Roy,et al.  Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Massimo Alioto,et al.  Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Volkan Kursun,et al.  FinFET domino logic with independent gate keepers , 2009, Microelectron. J..

[8]  Felipe S. Marques,et al.  Improving the methodology to build non-series-parallel transistor arrangements , 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

[9]  Jianping Hu,et al.  Optimization of dual-threshold independent-gate FinFETs for compact low power logic circuits , 2016, 2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO).

[10]  K. Endo,et al.  Independent-Double-Gate FinFET SRAM for Leakage Current Reduction , 2009, IEEE Electron Device Letters.

[11]  Sheldon B. Akers,et al.  Binary Decision Diagrams , 1978, IEEE Transactions on Computers.

[12]  Kartik Mohanram,et al.  Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Ali Assi,et al.  An efficient estimation of the ROBDD's complexity , 2006, Integr..

[14]  Volkan Kursun,et al.  Multi-Threshold Voltage FinFET Sequential Circuits , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[16]  Mayler G. A. Martins,et al.  Boolean factoring with multi-objective goals , 2010, 2010 IEEE International Conference on Computer Design.

[17]  Christel Baier,et al.  Genetic Algorithms for the Variable Ordering Problem of Binary Decision Diagrams , 2005, FOGA.

[18]  Yasuhiko Sasaki,et al.  Top-down pass-transistor logic design , 1996, IEEE J. Solid State Circuits.

[19]  V. Kursun,et al.  Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs , 2008, IEEE Transactions on Electron Devices.