An Efficient Algorithm for Finding a Universal Set of Testable Long Paths

In this paper, we focus on generation of a universal path candidate set U that contains testable long paths for delay testing. Some strategies are presented to speed up the depth first search procedure of U generation, targeting the reduction of sensitization criteria checking times. Experimental results illustrate that our approach achieves an 8X speedup on average in comparison with the traditional depth first search approach.

[1]  D. M. H. Walker,et al.  An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[2]  Melvin A. Breuer,et al.  New Validation and Test Problems for High Performance Deep Sub-micron VLSI Circuits , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[3]  David Blaauw,et al.  Statistical Timing Analysis: From Basic Principles to State of the Art , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Michael S. Hsiao,et al.  Using Global Structural Relationships of Signals to Accelerate SAT-based Combinational Equivalence Checking , 2004, J. Univers. Comput. Sci..

[5]  Huawei Li,et al.  Fast path selection for testing of small delay defects considering path correlations , 2010, 2010 28th VLSI Test Symposium (VTS).

[6]  Pallab Dasgupta,et al.  Event propagation for accurate circuit delay calculation using SAT , 2008, TODE.

[7]  Huawei Li,et al.  Testable Critical Path Selection Considering Process Variation , 2010, IEICE Trans. Inf. Syst..

[8]  Jinjun Xiong,et al.  Variation-aware performance verification using at-speed structural test and statistical timing , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[9]  Jing-Jia Liou,et al.  False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[10]  Robert C. Aitken,et al.  Nanometer Technology Effects on Fault Models for IC Testing , 1999, Computer.

[11]  S. Sahni,et al.  On path selection in combinational logic circuits , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[12]  Janak H. Patel,et al.  Finding a small set of longest testable paths that cover every gate , 2002, Proceedings. International Test Conference.

[13]  Kwang-Ting Cheng,et al.  Critical path selection for delay fault testing based upon a statistical timing model , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Keith Baker,et al.  Defect-based delay testing of resistive vias-contacts a critical evaluation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[16]  Lalit M. Patnaik,et al.  Line coverage of path delay faults , 2000, IEEE Trans. Very Large Scale Integr. Syst..