ESD dynamic methodology for diagnosis and predictive simulation of HBM/CDM events

A comprehensive ESD dynamic methodology is developed for failure diagnosis and predictive simulation of improvements. This methodology focuses on dynamic analysis including modeling of die-level metal grid, substrate grid and well-diode, package effective capacitance, and pogo pin. Real HBM and CDM application examples are illustrated.

[1]  Norman Chang,et al.  Efficient multi-domain ESD analysis and verification for large SoC designs , 2011, EOS/ESD Symposium Proceedings.

[2]  Jean-Jacques Hajjar,et al.  CDM event simulation in SPICE: A holistic approach , 2011, EOS/ESD Symposium Proceedings.

[3]  Theo Smedes,et al.  Full chip model of CMOS Integrated Circuits under Charged Device Model stress , 2004 .

[4]  M. Stockinger,et al.  Comprehensive ESD protection for flip-chip products in a dual gate oxide 65nm CMOS technology , 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

[5]  Doris Schmitt-Landsiedel,et al.  ESD full chip simulation: HBM and CDM requirements and simulation approach , 2008 .

[6]  M. Fakhruddin,et al.  Effect of flip-chip package parameters on CDM discharge , 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

[7]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[8]  Sung-Mo Kang,et al.  Chip-level simulation for CDM failures in multi-power ICs , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[9]  Dolphin Abessolo-Bidzo,et al.  Predictive CDM simulation approach based on tester, package and full integrated circuit modeling , 2011, EOS/ESD Symposium Proceedings.

[10]  T. Smedes,et al.  The impact of substrate resistivity on ESD protection devices , 2002, 2002 Electrical Overstress/Electrostatic Discharge Symposium.

[11]  Javier A. Salcedo,et al.  CDM ESD current characterization — Package variability effects and comparison to die-level CDM , 2009, 2009 31st EOS/ESD Symposium.