IDDQ testing: state of the art and future trends
暂无分享,去创建一个
Rosa Rodríguez-Montañés | Joan Figueras | Antoni Ferré | Josep Rius Vázquez | Eugeni Isern | J. Figueras | J. Rius | R. Rodríguez-Montañés | E. Isern | A. Ferré
[1] B. R. Bannister,et al. Testing mixed signal ASICs through the use of supply current monitoring , 1993, Proceedings ETC 93 Third European Test Conference.
[2] Chih-Wen Lu,et al. A fast and sensitive built-in current sensor for IDDQ testing , 1996, Digest of Papers 1996 IEEE International Workshop on IDDQ Testing.
[3] Kozo Kinoshita,et al. CIRCUIT DESIGN FOR BUILT-IN CURRENT TESTING , 1992, Proceedings International Test Conference 1992.
[4] Marcel Jacomet,et al. Fantestic: towards a powerful fault analysis and test pattern generator for integrated circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[5] John Paul Shen,et al. A CMOS fault extractor for inductive fault analysis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] John M. Acken,et al. Standard cell library characterization for setting current limits for I/sub DDQ/ testing , 1996, Digest of Papers 1996 IEEE International Workshop on IDDQ Testing.
[7] Alan Hales. A serially addressable, flexible current monitor for test fixture based I/sub DDQ//I/sub SSQ/ testing , 1994, Proceedings., International Test Conference.
[8] Robert C. Aitken,et al. Fault Location with Current Monitoring , 1991, 1991, Proceedings. International Test Conference.
[9] Yukiya Miura. Real-Time Current Testing for A/D Converters , 1996, IEEE Des. Test Comput..
[10] Wojciech Maly,et al. CMOS bridging fault detection , 1990, Proceedings. International Test Conference 1990.
[11] Claude Thibeault,et al. A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[12] Michele Favalli,et al. IDDQ TEST INVALIDATION BY BREAK FAULTS , 1996 .
[13] Dhiraj K. Pradhan,et al. Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets , 1980, IEEE Transactions on Computers.
[14] Tracy Larrabee,et al. Test Pattern Generation for Realistic Bridge Faults in CMOS ICs , 1991, 1991, Proceedings. International Test Conference.
[15] Wojciech Maly,et al. Design of ICs applying built-in current testing , 1992, J. Electron. Test..
[16] Wojciech Maly,et al. Built-in current testing-feasibility study , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[17] Jürgen Alt,et al. Test generation for I/sub DDQ/ testing and leakage fault detection in CMOS circuits , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.
[18] Antonio Rubio,et al. I/sub ddq/ secondary components in CMOS logic circuits preceded by defective stages affected by analogue type faults , 1991 .
[19] David L. Landis,et al. A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs , 1996, Proceedings of 14th VLSI Test Symposium.
[20] Wojciech Maly,et al. Current signatures for production testing [CMOS ICs] , 1996, Digest of Papers 1996 IEEE International Workshop on IDDQ Testing.
[21] R. Rodriguez-Montanes,et al. Estimation of the defective I/sub DDQ/ caused by shorts in deep-submicron CMOS ICs , 1998, Proceedings Design, Automation and Test in Europe.
[22] Wojciech Maly,et al. Realistic Fault Modeling for VLSI Testing , 1987, 24th ACM/IEEE Design Automation Conference.
[23] Michael Nicolaidis,et al. A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[24] Michael D. Ciletti,et al. QUIETEST: a quiescent current testing methodology for detecting leakage faults , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[25] Kaushik Roy,et al. Intrinsic leakage in low power deep submicron CMOS ICs , 1997, Proceedings International Test Conference 1997.
[26] Keith Baker,et al. Plug-and-play I/sub DDQ/ Testing for test fixtures , 1995, IEEE Design & Test of Computers.
[27] Yoshihiro Hashimoto,et al. High-Speed IDDQ Measurement Circuit , 1996 .
[28] Jerry Soden,et al. Test Considerations for Gate Oxide Shorts in CMOS ICs , 1986, IEEE Design & Test of Computers.
[29] Chenming Hu,et al. Future CMOS scaling and reliability , 1993, Proc. IEEE.
[30] Joan Figueras,et al. On estimating bounds of the quiescent current for I/sub DDQ/ testing , 1996, Proceedings of 14th VLSI Test Symposium.
[31] Yukiya Miura,et al. An IDDQ sensor circuit for low-voltage ICs , 1997, Proceedings International Test Conference 1997.
[32] Jaime Ramírez-Angulo. Low voltage current mirrors for built-in current sensors , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.
[33] W. H. Debany,et al. Coverage of Node Shorts Using Internal Access and Equivalence Classes , 1993, VLSI Design.
[34] Wojciech Maly,et al. Current Signatures for Production Testing , 1996 .
[35] Joan Figueras,et al. Proportional BIC sensor for current testing , 1992, J. Electron. Test..
[36] Melvin A. Breuer,et al. Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[37] Rosa Rodríguez-Montañés,et al. Bridges in sequential CMOS circuits: current-voltage signature , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[38] Wojciech Maly,et al. Built-in current testing , 1992 .
[39] Carver Mead. Scaling of MOS technology to submicrometer feature sizes , 1994, J. VLSI Signal Process..
[40] Antonio Rubio,et al. A built-in quiescent current monitor for CMOS VLSI circuits , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.
[41] Manoj Sachdev. Deep sub-micron I/sub DDQ/ testing: issues and solutions , 1997, Proceedings European Design and Test Conference. ED & TC 97.
[42] Robert H. Dennard,et al. CMOS scaling for high performance and low power-the next ten years , 1995, Proc. IEEE.
[43] J. Figueras,et al. I/sub DDQ/ test and diagnosis of CMOS circuits , 1995 .
[44] Yukiya Miura,et al. A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs , 1995, IEICE Trans. Inf. Syst..
[45] Scott F. Midkiff,et al. Test generation for IDDQ testing of bridging faults in CMOS circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[46] Josep Rius Vázquez,et al. Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments , 1996, J. Electron. Test..
[47] Maurizio Rebaudengo,et al. GALLO: a genetic algorithm for floorplan area optimization , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[48] Charles F. Hawkins,et al. THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS , 1991, 1991, Proceedings. International Test Conference.
[49] Antonio Rubio,et al. A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors , 1996, J. Electron. Test..
[50] Adit D. Singh,et al. Incorporating IDDQ testing in BIST: improved coverage through test diversity , 1994, Proceedings of IEEE VLSI Test Symposium.
[51] A.D. Singh. A comprehensive wafer oriented test evaluation (WOTE) scheme for the IDDQ testing of deep sub-micron technologies , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.
[52] Shyang-Tai Su,et al. Transient power supply current testing of digital CMOS circuits , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[53] Kenneth M. Wallquist. On the effect of I/sub SSQ/ testing in reducing early failure rate , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[54] Keith Baker,et al. Development of a class 1 QTAG monitor , 1994, Proceedings., International Test Conference.
[55] Rosa Rodríguez-Montañés,et al. Analysis of bridging defects in sequential CMOS circuits and their current testability , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.
[56] M. Ray Mercer,et al. Iddq testing for high performance CMOS-the next ten years , 1996, Proceedings ED&TC European Design and Test Conference.
[57] R. Rodríguez-Montañés,et al. Bridging defects resistance in the metal layer of a CMOS process , 1996, J. Electron. Test..
[58] Shyang-Tai Su,et al. Transient power supply current monitoring—A new test method for CMOS VLSI circuits , 1995, J. Electron. Test..
[59] P. K. Vasudev,et al. Si-ULSI with a scaled down future , 1998 .
[60] Irith Pomeranz,et al. Compact test generation for bridging faults under I/sub DDQ/ testing , 1995, Proceedings 13th IEEE VLSI Test Symposium.
[61] M. Roca,et al. Quiescent current testing of combinational circuits with bridging faults , 1992, Proceedings First Asian Test Symposium (ATS `92).
[62] Hiroshi Yokoyama,et al. A current testing for CMOS static RAMs , 1993, Records of the 1993 IEEE International Workshop on Memory Testing.
[63] Yashwant K. Malaiya,et al. Resolution Enhancement in IDDQ Testingfor Large ICs , 1994 .
[64] John M. Acken. Testing for Bridging Faults (Shorts) in CMOS Circuits , 1983, 20th Design Automation Conference Proceedings.
[65] J.H. Patel,et al. An efficient I/sub DDQ/ test generation scheme for bridging faults in CMOS digital circuits , 1996, Digest of Papers 1996 IEEE International Workshop on IDDQ Testing.
[66] Steven D. McEuen. Reliability benefits of IDDQ , 1992, J. Electron. Test..
[67] R. D. McLeod,et al. Built-in current mode circuits for I/sub ddq/ monitoring , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.
[68] Kuen-Jong Lee,et al. A high-speed low-voltage built-in current sensor , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.
[69] Michele Favalli,et al. CMOS design for improved IC testability , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[70] Jien-Chung Lo,et al. Testing the realistic bridging faults in CMOS circuits , 1996, Digest of Papers 1996 IEEE International Workshop on IDDQ Testing.
[71] Miquel Roca,et al. Current testability analysis of feedback bridging faults in CMOS circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[72] Charles F. Hawkins,et al. Quiescent power supply current measurement for CMOS IC defect detection , 1989 .
[73] Víctor H. Champac,et al. CURRENT VS. LOGIC TESTING OF GATE OXIDE SHORT, FLOATING GATE AND BRIDGING FAILURES IN CMOS , 1991, 1991, Proceedings. International Test Conference.
[74] Masanori Hamada,et al. The Effect of CMOS VLSI IDDq Measurement on Defect Level , 1995, IEICE Trans. Inf. Syst..
[75] Elizabeth M. Rudnick,et al. Sequential Circuit Test Generation in a Genetic Algorithm Framework , 1994, 31st Design Automation Conference.
[76] Víctor H. Champac,et al. IDDQ Testing of Opens in CMOS SRAMs , 1999, J. Electron. Test..
[77] Michael Nicolaidis,et al. Design of static CMOS self-checking circuits using built-in current sensing , 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.
[78] Antonio Rubio,et al. Quiescent current sensor circuits in digital VLSI CMOS testing , 1990 .
[79] Yoshio Murakami,et al. Separation and analysis of diffusion and generation components of pn junction leakage current in various silicon wafers , 1994 .
[80] Charles F. Hawkins,et al. IDDQ testing: A review , 1992, J. Electron. Test..
[81] Robert C. Aitken,et al. Diagnosis of leakage faults with IDDQ , 1992, J. Electron. Test..
[82] Glenn R. Case,et al. Analysis of actual fault mechanisms in CMOS logic gates , 1976, DAC '76.
[83] Kenneth M. Butler,et al. So what is an optimal test mix? A discussion of the SEMATECH methods experiment , 1997, Proceedings International Test Conference 1997.
[84] Paolo Prinetto,et al. GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[85] Elizabeth M. Rudnick,et al. Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits , 1996, Proceedings of 14th VLSI Test Symposium.
[86] Charles F. Hawkins,et al. Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs , 1985, ITC.
[87] M. Ray Mercer,et al. Iddq test: sensitivity analysis of scaling , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[88] H. Yamazaki,et al. IDDQ testability of flip-flop structures , 1996, Digest of Papers 1996 IEEE International Workshop on IDDQ Testing.
[89] Josep Rius Vázquez,et al. Detecting I/sub DDQ/ defective CMOS circuits by depowering , 1995, Proceedings 13th IEEE VLSI Test Symposium.
[90] Shyh-Jye Jou,et al. An I/sub DDQ/ based built-in concurrent test technique for interconnects in a boundary scan environment , 1994, Proceedings., International Test Conference.
[91] Yves Crouzet,et al. Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability , 1980, IEEE Transactions on Computers.
[92] Premachandran R. Menon,et al. A Practical Approach to Fault Simulation and Test Generation for Bridging Faults , 1985, IEEE Transactions on Computers.
[93] P.C. Maxwell,et al. A simulation-based method for estimating defect-free I/sub DDQ/ , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.
[94] João Paulo Teixeira,et al. Physical DFT for High Coverage of Realistic Faults , 1992, Proceedings International Test Conference 1992.
[95] T. Maeda,et al. Sequential circuit test generation for IDDQ testing of bridging faults , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.
[96] Manoj Sachdev. I/sub DDQ/ and voltage testable CMOS flip-flop configurations , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[97] Juan A. Carrasco,et al. Synthesis of IDDQ-Testable Circuits: Integrating Built-in Current Sensors , 1995, DAC 1995.
[98] Antonio Rubio,et al. Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[99] Sreejit Chakravarty,et al. Simulation and generation of IDDQ tests for bridging faults in combinational circuits , 1993, VTS.
[100] Yashwant K. Malaiya,et al. A New Fault Model and Testing Technique for CMOS Devices , 1982, International Test Conference.
[101] C. Martinez,et al. Compact BIC sensor for I/sub ddq/ testing of CMOS circuits , 1993 .
[102] Wojciech Maly,et al. Test generation for current testing , 1989, [1989] Proceedings of the 1st European Test Conference.
[103] Kenneth M. Wallquist,et al. A General Purpose IDDQ Measurement Circuit , 1993 .
[104] Jos van Sas,et al. An off-chip IDDq current measurement unit for telecommunication ASICs , 1994, Proceedings., International Test Conference.
[105] S. M. Sze,et al. Physics of semiconductor devices , 1969 .
[106] J. Ramirez-Angulo,et al. High speed IDDQ current sensors for VLSI system testing , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
[107] J. Figueras,et al. Test generation with high coverages for quiescent current test of bridging faults in combinational circuits , 1993, Proceedings of IEEE International Test Conference - (ITC).
[108] M. Renovell,et al. Topology dependence of floating gate faults in MOS integrated circuits , 1986 .
[109] H. T. Vierhaus,et al. CMOS overcurrent test: BIC-monitor design, circuit partitioning and test patterns , 1994, Proceedings of Twentieth Euromicro Conference. System Architecture and Integration.
[110] Robert C. Aitken,et al. IDDQ and AC scan: the war against unmodelled defects , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[111] A.P. Jayasumana,et al. Limitations of built-in current sensors (BICS) for I/sub DDQ/ testing , 1993, Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS).
[112] Wojciech Maly,et al. Testing oriented analysis of CMOS ICs with opens , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[113] J. M. Soden,et al. Electrical properties and detection methods for CMOS IC defects , 1989, [1989] Proceedings of the 1st European Test Conference.
[114] Sreejit Chakravarty,et al. Fast algorithms for computing I/sub DDQ/ tests for combinational circuits , 1996, Proceedings of 9th International Conference on VLSI Design.
[115] Jacob A. Abraham,et al. FAULT CHARACTERIZATION OF VLSI MOS CIRCUITS. , 1982 .
[116] Mark W. Levi,et al. CMOS Is Most Testable , 1981, International Test Conference.
[117] Sreejit Chakravarty,et al. A study of I/sub DDQ/ subset selection algorithms for bridging faults , 1994, Proceedings., International Test Conference.
[118] Charles F. Hawkins,et al. IDDQ Testing: Issues Present and Future , 1996, IEEE Des. Test Comput..
[119] Anura P. Jayasumana,et al. The effect of built-in current sensors (BICS) on operational and test performance /spl lsqb/CMOS ICs/spl rsqb/ , 1994, Proceedings of 7th International Conference on VLSI Design.
[120] M. Rencz,et al. Cooling as a possible way to extend the usability of I/sub DDQ/ testing , 1997 .
[121] Keith Baker. QTAG: a standard for test fixture based I/sub DDQ//I/sub SSQ/ monitors , 1994, Proceedings., International Test Conference.
[122] L. Balado,et al. Quiescent current estimation for current testing , 1992, [1992] Proceedings The European Conference on Design Automation.
[123] M. Hashizume,et al. A current sensing circuit for feedback bridging faults , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.
[124] Kozo Kinoshita,et al. A case study of mixed-signal integrated circuit testing: an application of current testing using the upper limit and the lower limit , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.
[125] Scott F. Midkiff,et al. ON TEST GENERATION FOR I/sub DDQ/ TESTING OF BRIDGING FAULTS IN CMOS CIRCUITS , 1991, 1991, Proceedings. International Test Conference.
[126] A.P. Jayasumana,et al. A bipartite, differential I/sub DDQ/ testable static RAM design , 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.
[127] S. Beckers,et al. The spidermask: a new approach for yield monitoring using product adaptable test structures , 1990, International Conference on Microelectronic Test Structures.
[128] Jien-Chung Lo,et al. A 2-ns detecting time, 2- mu m CMOS built-in current sensing circuit , 1993 .
[129] Kazuo Horie,et al. A complete substrate current model including band-to-band tunneling current for circuit simulation , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..