Adder methodology and design using probabilistic multiple carry estimates

A novel approach for designing estimated carry adders for use in asynchronous circuits is presented. It demonstrates that by using statistical probability of a carry being in a particular state, a 32-bit adder can be constructed in which for the majority of additions there is an improvement in the speed performance of the adder. This methodology shows that each time an additional carry is introduced for carry prediction there is a 50% gain in speed performance over the previous 32-bit addition. This novel adder methodology significantly reduces the addition time, and through simulation and design it has been shown that the 32-bit ESTC adder using multiple carries can dramatically achieve speed and/or area advantages over existing adder circuits. For example using four carries for prediction, comparisons in terms of delay–area product show performance savings of more than 41% over the carry select adder with ripple adder elements, and more than 26% over both carry lookahead and carry select adders based on carry lookahead elements.

[1]  Gilles Sicard,et al.  Low-Power Asynchronous A/D Conversion , 2002, PATMOS.

[2]  M. Franklin,et al.  Performance comparison of asynchronous adders , 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.

[3]  Chingwei Yeh,et al.  Fast and compact dynamic ripple carry adder design , 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

[4]  Scott Hauck,et al.  Asynchronous design methodologies: an overview , 1995, Proc. IEEE.

[5]  Mao Zhi-gang,et al.  A 64 bit parallel CMOS adder for high performance processors , 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

[6]  Mititada Morisue,et al.  Design of a multiple-operand redundant binary adder , 2002, Systems and Computers in Japan.

[7]  庄司 正一,et al.  CMOS digital circuit technology , 1988 .

[8]  David Kinniment.  An evaluation of asynchronous addition , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Reza Hashemian.  A new design for high speed and high-density carry select adders , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[10]  Ran Ginosar,et al.  Average-case optimized technology mapping of one-hot domino circuits , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[11]  Stephen H. Unger,et al.  Self-Timed Carry-Lookahead Adders , 2000, IEEE Trans. Computers.

[12]  Orest J. Bedrij.  Carry-Select Adder , 1962, IRE Trans. Electron. Comput..

[13]  Chenn-Jung Huang,et al.  A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic , 2003 .

[14]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[15]  Mary Jane Irwin,et al.  Area-time-power tradeoffs in parallel adders , 1996 .

[16]  Steven M. Nowick.  Design of a low-latency asynchronous adder using speculative completion , 1996 .

[17]  Peter A. Beerel.  Asynchronous circuits: an increasingly practical design solution , 2002, Proceedings International Symposium on Quality Electronic Design.

[18]  Oliver R. Hinton,et al.  Probabilistic carry state estimate for improved asynchronous adder performance , 2001 .

[19]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .

[20]  Young-Hyun Jun,et al.  CMOS differential logic family with self-timing and charge-recycling for high-speed and low-power VLSI , 2003 .

[21]  V. Akella,et al.  Design and analysis of asynchronous adders , 1998 .

[22]  M.-J. Hsiao,et al.  Carry-select adder using single ripple-carry adder , 1998 .

[23]  Steven M. Nowick,et al.  Fine-grain pipelined asynchronous adders for high-speed DSP applications , 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.