Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs

Although 3-D floorplanning has been studied widely, routability which is a very important issue in modern integrated circuit (IC) designs is rarely discussed. Floorplanning in 3-D ICs is much difficult than that in 2-D ICs because of large difference in sizes between modules and through silicon vias (TSVs), which are key components in 3-D ICs. And the locations of TSVs have great impact on wirelength and routability in resulting floorplans. Hence, this paper proposes a TSV-aware 3-D floorplanning methodology which can consider wirelength and routability at the same time under the fixed-outline constraint. Unlike most of previous works which completely apply the simulated annealing algorithm, our methodology mainly apply deterministic algorithms to resolve the problem. Thus, our approach is more efficient and flexible than previous works. Experimental results have demonstrated that the proposed methodology can significantly reduce routing congestion in 3-D ICs with a slight increase in wirelength.

[1]  Evangeline F. Y. Young,et al.  Multi-bend bus driven floorplanning , 2005, ISPD '05.

[2]  Yuan Xie,et al.  Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[3]  Jai-Ming Lin,et al.  F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Evangeline F. Y. Young,et al.  Planning Massive Interconnects in 3-D Chips , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Hai Zhou,et al.  3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits , 2007, ICCAD 2007.

[6]  Sung Kyu Lim,et al.  Block-level 3D IC design with through-silicon-via planning , 2012, 17th Asia and South Pacific Design Automation Conference.

[7]  Chris C. N. Chu,et al.  FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Jason Cong,et al.  A thermal-driven floorplanning algorithm for 3D ICs , 2004, ICCAD 2004.

[9]  Yao-Wen Chang,et al.  Temporal floorplanning using 3D-subTCG , 2004 .

[10]  Jens Lienig,et al.  Investigating modern layout representations for improved 3d design automation , 2011, GLSVLSI '11.

[11]  Ting-Chi Wang,et al.  Through-Silicon Via Planning in 3-D Floorplanning , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Yici Cai,et al.  Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  K. Warner,et al.  Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[14]  Sung Kyu Lim,et al.  High-density integration of functional modules using monolithic 3D-IC technology , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

[15]  Wei Zhong,et al.  Whitespace insertion for through-silicon via planning on 3-D SoCs , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[16]  Ting-Chi Wang,et al.  Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Sung Kyu Lim,et al.  Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Sheqin Dong,et al.  3D CBL: an efficient algorithm for general 3D packing problems , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

[19]  Yoji Kajitani,et al.  The 3 D-Packing by Meta Data Structure and Packing Heuristics , 2000 .

[20]  Mohammad A. Ahmed,et al.  3D floorplanning with nets-to-TSVs assignment , 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

[21]  O. Nelles,et al.  An Introduction to Optimization , 1996, IEEE Antennas and Propagation Magazine.

[22]  Vassilios Gerousis.  Physical design implementation for 3D IC: methodology and tools , 2010, ISPD '10.

[23]  A. Toffoli,et al.  Advances in 3D CMOS sequential integration , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[24]  Chris C. N. Chu,et al.  DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[25]  Sung Kyu Lim,et al.  A study of Through-Silicon-Via impact on the 3D stacked IC layout , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[26]  Jai-Ming Lin,et al.  UFO: unified convex optimization algorithms for fixed-outline floorplanning , 2010, ASP-DAC.

[27]  Sung Kyu Lim,et al.  Power benefit study for ultra-high density transistor-level monolithic 3D ICs , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[28]  Andrew B. Kahng,et al.  Classical floorplanning harmful? , 2000, ISPD '00.

[29]  Eric Beyne,et al.  The 3-D Interconnect Technology Landscape , 2016, IEEE Design & Test.

[30]  Jong-Wha Chong,et al.  A novel congestion estimation model and congestion aware floorplan for 3D ICs , 2012, 2012 International Conference on Innovation Management and Technology Research.

[31]  Evangeline F. Y. Young,et al.  Fixed-outline thermal-aware 3D floorplanning , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[32]  Erich Barke,et al.  Improving 3D-Floorplanning using smart selection operations in meta-heuristic optimization , 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

[33]  Takeshi Yoshimura,et al.  Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints , 2010, Integr..

[34]  Yao-Wen Chang,et al.  NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[35]  Ding-Ming Kwai,et al.  CAD reference flow for 3D via-last integrated circuits , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[36]  Liang Deng,et al.  Floorplanning for 3-D VLSI design , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[37]  Yao-Wen Chang,et al.  Temporal floorplanning using the T-tree formulation , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..