论文信息 - Impact of package parasitics on the EMC performance of smart power SoCs

Impact of package parasitics on the EMC performance of smart power SoCs

The paper deals with the propagation of EMI in Smart Power SoCs through high frequency parasitic paths, i.e. silicon substrate, and it focuses on the interaction between on-chip parasitic capacitors and package parasitic elements, that negatively affects IC electromagnetic emission. The paper highlights such unwanted parasitic effects through computer simulations and experimental test results. Finally, a new grounding scheme to improve the EMC performance of such integrated circuits is presented.

Franco Fiori | Marco Merlin

[1] Paolo Stefano Crovetti,et al. Efficient BEM-based substrate network extraction in silicon SoCs , 2008, Microelectron. J..

[2] Bruno Murari,et al. Smart power ICs : technologies and applications , 2002 .

[3] Francesco Musolino,et al. Comparative measurements and analysis of electromagnetic emissions of synchronous and asynchronous processors , 2008 .

[4] Franco Fiori. Reducing the Electromagnetic Emissions of Smart Power System-on-Chips by Design , 2009, 2009 20th International Zurich Symposium on Electromagnetic Compatibility.

[5] P. Larsson. Resonance and damping in CMOS circuits with on-chip decoupling capacitance , 1998 .

[6] Leonardo Reyneri,et al. Designing low electro magnetic emissions circuits through clock skew optimization , 2002, 9th International Conference on Electronics, Circuits and Systems.

[7] H. De Man,et al. Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).