CONNECT: Fast Flexible FPGA-Tuned Networks-on-Chip

In this paper we present CONNECT, a exible NoC architecture and RTL generation engine for fast, FPGA-tuned Networks-on-Chip (NoCs). The CONNECT NoC architecture embodies a set of FPGA-motivated design principles that uniquely inuence key NoC design decisions, such as topology, link width, router pipeline depth, network buer sizing, and ow control. The exibility, lightweight nature and high performance of CONNECT-based NoCs makes them ideal candidates for use in FPGA-based research studies. We evaluate CONNECT against a high-quality publicly available synthesizable RTL-level NoC design intended for ASICs. Our results show a signicant gain in specializing NoC design decisions to FPGAs’ unique mapping and operating characteristics. For example, in the case of a 4x4 mesh conguration evaluated using a set of synthetic trac patterns, we obtain comparable or better performance than the state-of-the-art NoC while reducing logic resource cost by 58%, or alternatively, achieve 3-4x better performance for approximately the same logic resource usage. To demonstrate CONNECT’s exibility and extensive design space coverage, we also report synthesis and network performance results for a variety of dierent CONNECT networks. This paper is based on [13] previously published at FPGA 2012.