PCI-X Protocol

This chapter discusses that PCI-X constitutes an extensive set of enhancements to the basic PCI protocol, like revised command protocol emphasizing a distinction between DWORD and burst transactions; an Attribute phase in each transaction to identify the initiator of the transaction; split transaction whereby a request is completely decoupled from the response, PCI-X Split Transactions replace conventional PCI's Retry; An error correction protocol that allows single bit errors to be corrected automatically; source synchronous data transfers that yield up to 4 gigabytes of bandwidth. Source synchronous transfers implement either two or four data subphases per clock cycle; Device ID Messaging that allows a device to talk directly to another device outside of the normal bus address spaces, the target of such a transaction may be explicitly specified by bus, device and function number or implicitly as the host bridge; and a 16-bit interface optimized for embedded applications.