Low power memristor-based ReRAM design with Error Correcting Code

The emerging memristor-based Resistive RAM (ReRAM) has shown great potential as one of the most promising memory technologies, with the unique properties such as high density, low-power, good-scalability, and non-volatility. However, as the process technology scales, the process variation will cause the deviation of the actual electrical behavior of memristor. Recently, researchers have observed that the probability of a single ReRAM cell switching successfully follows a function of the logarithm of the total programming time. As a result, the uncertainty of the electrical behavior results in different degrees of error rates in ReRAM-based memory. Traditional ECC (Error Correcting Code) design for conventional DRAM memory is used to detect and correct the errors in the memory system. In this paper, based on the mathematical analysis of the error patterns in memristor-based ReRAM and the study of ECC designs, we proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both the MOS based and cross-point based memristor ReRAM designs. In addition, the performance/power/area overhead of the proposed design options is also evaluated in detail.