Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor

Hierarchical power distribution with a power tree has been developed. The key features are power tree management rules and a distributed common power-domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a fine-grained clock gating. Leakage currents of a 1,000,000-gate power domain were effectively reduced to 1/4,000 in multi-CPU SoCs with minimal area overhead.

[1]  T. Hattori,et al.  Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[2]  Kenji Hirose,et al.  A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[3]  Y. Yasu,et al.  A resume-standby application processor for 3G cellular phones , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[4]  Y. Kanno.  μI/O Architecture for 0.13-um Wide-Voltage-Range System-on-a-Package (SoP) Designs , 2002 .

[5]  Uming Ko,et al.  90nm low leakage SoC design techniques for wireless applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[6]  S. Shimada,et al.  Low-power embedded SRAM modules with expanded margins for writing , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[7]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.