Implementing a Petri Net Specification in a FPGA Using VHDL

This paper discusses how the FPGA architectures affect the implementation of Petri net specifications.Taking into consideration the observations from that study, a method is developed for obtaining VHDL descriptions amenable to synthesis, and tested against other standard methods of implementation. These results have relevance in the integration of access technologies to high-speed telecommunication networks, where FPGAs are excellent implementation platforms.