Partitioned n-detection test generation

We describe a method for improving the quality of <i>n</i>-detection test sets. Unlike earlier methods for achieving the same goal, the proposed method is based on the conventional definition of the number of detections and uses a conventional <i>n</i>-detection test generation process. Under the proposed method, the set of target faults is partitioned into two or more subsets. <i>n</i>-detection test generation is carried out for each subset separately. The resulting test sets are combined into a single test set. Partitioning causes more faults to be targeted directly, and fewer faults to be dropped due to accidental detection. The fault subsets can be selected based on detection conditions of common defects. In this work we partition the set of faults into a subset that consists of all the stuck-at 0 faults, and a subset that consists of all the stuck-at 1 faults. We demonstrate through experimental results that for the same test set size, partitioning the set of faults improves the coverage of untargeted faults (non-feedback four-way bridging faults) compared to <i>n</i>-detection test generation for the unpartitioned set of faults.

[1]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[2]  Michel Renovell,et al.  Electrical analysis and modeling of floating-gate fault , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Venkatram Krishnaswamy,et al.  A study of bridging defect probabilities on a Pentium (TM) 4 CPU , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[4]  Edward J. McCluskey,et al.  Analysis of pattern-dependent and timing-dependent failures in an experimental test chip , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[5]  Gang Chen,et al.  Defect aware test patterns , 2005, Design, Automation and Test in Europe.

[6]  R. D. Blanton,et al.  Multiple-detect ATPG based on physical neighborhoods , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[7]  Edward J. McCluskey,et al.  An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[8]  Alejandro Girón,et al.  Test of interconnection opens considering coupling signals , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[9]  Víctor H. Champac,et al.  Detectability conditions for interconnection open defects , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[10]  Enamul Amyeen,et al.  An experimental study of N-detect scan ATPG patterns on a processor , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[11]  Haluk Konuk Voltage- and current-based fault simulation for interconnect open defects , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Robert C. Aitken,et al.  Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds , 1993, Proceedings of IEEE International Test Conference - (ITC).

[13]  R. Rodriguez-Montanes,et al.  Electrical and topological characterization of interconnect open defects , 2005, Proceedings. 2005 IEEE International Workshop on Current and Defect Based Testing, 2005. DBT 2005..

[14]  M. Ray Mercer,et al.  Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[15]  Sandip Kundu,et al.  Defect-Based Test : A Key Enabler for Successful Migration to Structural Test , 1999 .

[16]  Daniel Arumí,et al.  Defective behaviours of resistive opens in interconnect lines , 2005, European Test Symposium (ETS'05).

[17]  Janusz Rajski,et al.  Impact of multiple-detect test patterns on product quality , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[18]  Irith Pomeranz,et al.  Compact test sets for high defect coverage , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Irith Pomeranz,et al.  Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[20]  Wojciech Maly,et al.  Testing oriented analysis of CMOS ICs with opens , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[21]  Siyad C. Ma,et al.  A comparison of bridging fault simulation methods , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[22]  Irith Pomeranz,et al.  Forming N-detection test sets without test generation , 2007, TODE.

[23]  F. Joel Ferguson,et al.  An unexpected factor in testing for CMOS opens: the die surface , 1996, Proceedings of 14th VLSI Test Symposium.

[24]  André Ivanov,et al.  Testing for floating gates defects in CMOS circuits , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).