论文信息 - Standard Cell Layout Synthesis for Row-Based Placement and Routing of RSFQ and AQFP Logic Families

Standard Cell Layout Synthesis for Row-Based Placement and Routing of RSFQ and AQFP Logic Families

In this work under the IARPA SuperTools program we developed a layout synthesis tool with scripting support. The user specifies the relative positions of Josephson junctions and inductances constrained by a user-defined cell height and cell width. Tight integration with the three-dimensional inductance extraction tool, InductEx, allows inductances to be automatically generated while meeting reasonable design values. Based on these user inputs, the tool can synthesize the physical layout of logic cells for multiple SFQ circuit technologies according to design rules and layer parameters. Furthermore, it enables the straightforward regeneration of entire cell libraries when design rules change or when libraries have to be redesigned for more advanced fabrication processes. We describe the methodology of our synthesis tool and show the results applied to both RSFQ and AQFP logic families.

[1] Naoki Takeuchi,et al. Adiabatic quantum-flux-parametron cell library adopting minimalist design , 2015 .

[2] Alireza Shafaei,et al. An Integrated Row-Based Cell Placement and Interconnect Synthesis Tool for Large SFQ Logic Circuits , 2017, IEEE Transactions on Applied Superconductivity.

[3] V. Semenov,et al. Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process With 8 Niobium Layers , 2014, IEEE Transactions on Applied Superconductivity.

[4] Ruben van Staden,et al. Layout versus Schematic with Design/Magnetic Rule Checking for Superconducting Integrated Circuit Layouts , 2019, 2019 IEEE International Superconductive Electronics Conference (ISEC).

[5] Massoud Pedram,et al. ColdFlux Superconducting EDA and TCAD Tools Project: Overview and Progress , 2019, IEEE Transactions on Applied Superconductivity.

[6] Naoki Takeuchi,et al. Adiabatic quantum-flux-parametron cell library designed using a 10 kA cm−2 niobium fabrication process , 2017 .

[7] Coenrad J. Fourie,et al. Full-Gate Verification of Superconducting Integrated Circuit Layouts With InductEx , 2015, IEEE Transactions on Applied Superconductivity.