Extraction error diagnosis and correction in high-performance designs

Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires the extraction of a gate-level (logic) model from the transistor level representation of the circuit under test. Logic extraction is an error prone process due to extraction tool limitations and due to the human interference. Errors introduced by extraction require manual debugging, a resource intensive and time consuming task. This paper presents a set of extraction errors typical in an industrial environment. It also proposes an automated solution to extraction error diagnosis und correction. Experiments on circuits with similar architecture to that of high speed custom-made industrial blocks are conducted to confirm the fitness of the approach.

[1]  Masahiro Fujita,et al.  Modeling the unknown! Towards model-independent fault and error diagnosis , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[2]  Janak H. Patel,et al.  New Techniques for Deterministic Test Pattern Generation , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[3]  D. M. H. Walker,et al.  Simulation-based design error diagnosis and correction in combinational digital circuits , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[4]  Hiroshi Takahashi,et al.  Incremental diagnosis of multiple open-interconnects , 2002, Proceedings. International Test Conference.

[5]  Shi-Yu Huang.  Towards the logic defect diagnosis for partial-scan designs , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[6]  Ibrahim N. Hajj,et al.  Design error diagnosis and correction via test vector simulation , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[8]  W. Kent Fuchs,et al.  A deductive technique for diagnosis of bridging faults , 1997, ICCAD 1997.

[9]  Robert C. Aitken.  Modeling the Unmodelable: Algorithmic Fault Diagnosis , 1997, IEEE Des. Test Comput..

[10]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[11]  Thomas J. Snethen,et al.  Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[12]  Shi-Yu Huang,et al.  Fault-simulation based design error diagnosis for sequential circuits , 1998, DAC.

[13]  Andreas G. Veneris,et al.  Incremental diagnosis and correction of multiple faults and errors , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.