A Novel High Speed Dynamic Comparator with Low Power Dissipation and Low Offset

A new fully differential CMOS dynamic comparator using positive feedback suitable for pipeline A/D converters with low power dissipation, low offset, low noise and high speed is proposed. Inputs are reconfigured from typical differential pair comparator such that near equal current distribution in the input transistors can be achieved for a meta stable point of the comparator. Restricted signal swing clock for the tail current is also used to ensure constant currents in the differential pairs. Nearly 18mV offset voltage is easily achieved with the proposed structure making it favorable for flash and pipeline data conversion applications. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources, has a small power dissipation, less hysteresis band, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Test structures of the comparators, designed in GPDK 90 nm are measured to determine offset power dissipation and speed with 1.8 V are compared and the superior features of the proposed comparator are established.

[1]  Behzad Razavi,et al.  Design techniques for high-speed, high-resolution comparators , 1992 .

[2]  Degang Chen,et al.  Adjustable hysteresis CMOS Schmitt triggers , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[3]  Shahriar Mirabbasi,et al.  A 0.35 /spl mu/m CMOS comparator circuit for high-speed ADC applications , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[4]  Degang Chen,et al.  A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs , 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

[5]  Yu Lin,et al.  kT/C constrained optimization of power in pipeline ADCs , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[6]  F. E. Terman,et al.  Integrated Electronics: Analog and Digital Circuits and Systems , 1972 .

[7]  Hai Phuong. Le,et al.  Performance analysis of optimised CMOS comparator , 2003 .

[8]  Kari Halonen,et al.  A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[9]  Kari Halonen,et al.  CMOS dynamic comparators for pipeline A/D converters , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[10]  N. Joel.  Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers , 2004 .

[11]  Byung-Moo Min,et al.  A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC , 2003, IEEE J. Solid State Circuits.

[12]  T.W. Matthews,et al.  A simulation method for accurately determining DC and dynamic offsets in comparators , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

[13]  Paul R. Gray,et al.  A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.