A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems

Nano-Electro-Mechanical-Systems (NEMS) are a technological solution for building miniature systems which can be beneficial in terms of safety, efficacy, or convenience. Thus investigation is necessary for their usefulness in drug delivery. In order to be an effective and reliable implantable system the DDNEMS (Drug Delivery Nano-Electro-Mechanical-System) should have low power dissipation, fault tolerance, and reconfigurability capabilities. In this paper we introduce a DDNEMS architecture, identify its major components, and propose the design of the crucial component universal (voltage) level converter (ULC). The ULC is a unique component that will reduce dynamic power and leakage of DDNEMS while facilitating its reconfigurability. The ULC is capable of performing level-up and level-down conversions and can block an input signal. We have prototyped a ULC using 32nm high-k/metal-gate nano-CMOS technology with dual-VTh technique. The robustness of the design is tested by carrying out three types of analysis, namely: parametric, load and power. It is observed that the ULC produces a stable output for voltages as low as 0.35V and loads varying from 50fF to 120fF. The average power dissipation of the proposed level converter with a 82fF capacitive load is 5µW.

[1]  Borivoje Nikolic,et al.  Level conversion for dual-supply systems , 2004 .

[2]  K. Onishi,et al.  Fabrication of high quality ultra-thin HfO/sub 2/ gate dielectric MOSFETs using deuterium anneal , 2002, Digest. International Electron Devices Meeting,.

[3]  K. Tanaka,et al.  Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[4]  Saraju P. Mohanty,et al.  A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs , 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

[5]  G. Dewey,et al.  30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[6]  Bin-Da Liu,et al.  A new level converter for low-power applications , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[7]  Mark C. Johnson,et al.  Design and optimization of dual-threshold circuits for low-voltage low-power applications , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Aaas News,et al.  Book Reviews , 1893, Buffalo Medical and Surgical Journal.

[9]  Yu Cao,et al.  Predictive Technology Model for Nano-CMOS Design Exploration , 2006, 2006 1st International Conference on Nano-Networks and Workshops.

[10]  Saraju P. Mohanty,et al.  Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[11]  Dirk Timmermann,et al.  Design of mixed gates for leakage reduction , 2007, GLSVLSI '07.

[12]  Saraju P. Mohanty,et al.  A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-V DD SoCs , 2008, ISQED 2008.

[13]  F. Farbiz,et al.  Using Level Restoring Method for Dual Supply Voltage , 2006, 2006 7th International Symposium on Antennas, Propagation & EM Theory.

[14]  Robert Langer,et al.  Application of Micro- and Nano-Electromechanical Devices to Drug Delivery , 2006, Pharmaceutical Research.

[15]  Yu Cao,et al.  New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.