Efficient Implementation of Single Error Correction and Double Error Detection Code with Check Bit Pre- computation for Memories

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit precomputation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weightcolumn code during the write operation and is designed by replacing 0’s with 1’s at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the oddweight-column code, the implementation based on the proposed SEC-DED code with check bit precomputation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

[1]  M. Y. Hsiao,et al.  A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .

[2]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[3]  Ad J. van de Goor,et al.  Soft faults and the importance of stresses in memory testing , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[4]  藤原 英二,et al.  Code design for dependable systems : theory and practical applications , 2006 .

[5]  Nacer-Eddine Zergainoh,et al.  Eliminating speed penalty in ECC protected memories , 2011, 2011 Design, Automation & Test in Europe.

[6]  M. Chiani.  Error Detecting and Error Correcting Codes , 2012 .

[7]  Deog-Kyoon Jeong,et al.  A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring , 2012 .

[8]  Richard W. Hamming,et al.  Error detecting and error correcting codes , 1950 .

[9]  Tae Geun Kim,et al.  Comparative investigation of endurance and bias temperature instability characteristics in metal-Al 2 O 3 - nitride-oxide-semiconductor (MANOS) and semiconductor-oxide-nitride-oxide-semiconductor (SONOS) charge trap flash memory , 2012 .

[10]  Hongil Yoon,et al.  High Speed, Minimal Area, and Low Power SEC Code for DRAMs with Large I/O Data Widths , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[11]  C. Luchini,et al.  [High speed]. , 1969, Revista De La Escuela De Odontologia, Universidad Nacional De Tucuman, Facultad De Medicina.

[12]  P. K. Lala,et al.  Single error correcting and double error detecting coding scheme , 2005 .

[13]  S. Simmons,et al.  A study on the VLSI implementation of ECC for embedded DRAM , 2003, CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436).

[14]  Sanguhn Cha,et al.  A Low-Power ECC Check Bit Generator Implementation in DRAMs , 2006 .

[15]  Zeljko Zilic,et al.  Design and implementation of error detection and correction circuitry for multilevel memory protection , 2002, Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic.

[16]  P E Dodd,et al.  Current and Future Challenges in Radiation Effects on CMOS Electronics , 2010, IEEE Transactions on Nuclear Science.