RC-In-RC-Out model order reduction via node merging

In this paper, we introduce a method for realizable reduction of extracted RC netlists by merging nodes. This method can achieve high reduction (reaching 96%) with high accuracy and can be used to complement existing techniques of realizable reduction such as TICER [6]. The method preserves sparsity; has controllable accuracy and can result in lossless reduction (exact reduction) for certain circuits. The node merging translates to a simple matrix operation and thus can be easily adopted commercially and realized in CAD tools.

[1]  Mattan Kamon,et al.  A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits , 1996, Proceedings of International Conference on Computer Aided Design.

[2]  Mihai Iordache,et al.  Model order reduction by a projection technique implemented on state equations , 2009, 2009 International Symposium on Signals, Circuits and Systems.

[3]  Yehea I. Ismail,et al.  Realizable reduction of interconnect circuits including self and mutual inductances , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Jacob K. White,et al.  A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits , 1996, ICCAD 1996.

[5]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.

[6]  Bernard N. Sheehan,et al.  TICER: Realizable reduction of extracted RC circuits , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[7]  Yehea I. Ismail,et al.  DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Charlie Chung-Ping Chen,et al.  RC-in RC-out model order reduction accurate up to second order moments , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[9]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1998, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[10]  Janne Roos,et al.  PartMOR: Partitioning-Based Realizable Model-Order Reduction Method for RLC Circuits , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Janne Roos,et al.  Realizable reduction of interconnect models with dense coupling , 2013, 2013 European Conference on Circuit Theory and Design (ECCTD).

[12]  Zuochang Ye,et al.  Sparse Implicit Projection (SIP) for reduction of general many-terminal networks , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[13]  Yehea I. Ismail,et al.  Realizable RLCK circuit crunching , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).