Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor
暂无分享,去创建一个
[1] Wei Wang,et al. Design of U-Shape Channel Tunnel FETs With SiGe Source Regions , 2014, IEEE Transactions on Electron Devices.
[2] Balwinder Raj,et al. Design and analysis of dynamically configurable electrostatic doped carbon nanotube tunnel FET , 2019, Microelectron. J..
[3] S. S. Chauhan,et al. A novel vertical tunneling based Ge-source TFET with enhanced DC and RF characteristics for prospect low power applications , 2019, Microelectronic Engineering.
[4] Stefan Kubicek,et al. Deposition of HfO2 on germanium and the impact of surface pretreatments , 2004 .
[5] Woo Young Choi,et al. Demonstration of L-Shaped Tunnel Field-Effect Transistors , 2016, IEEE Transactions on Electron Devices.
[6] Xichun Luo,et al. Promising Lithography Techniques for Next-Generation Logic Devices , 2018 .
[7] S. S. Chauhan,et al. Insights into the DC, RF/Analog and linearity performance of vertical tunneling based TFET for low-power applications , 2019, Microelectronic Engineering.
[8] Saibal Mukhopadhyay,et al. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.
[9] Byung-Gook Park,et al. Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec , 2007, IEEE Electron Device Letters.
[10] B. Raj,et al. Analysis of electrostatic doped Schottky barrier carbon nanotube FET for low power applications , 2016, Journal of Materials Science: Materials in Electronics.
[11] S. Saurabh,et al. Fundamentals of Tunnel Field-Effect Transistors , 2016 .
[12] Kaikai Xu. Silicon electro-optic micro-modulator fabricated in standard CMOS technology as components for all silicon monolithic integrated optoelectronic systems , 2021, Journal of Micromechanics and Microengineering.
[13] Hyungcheol Shin,et al. Scalable embedded Ge-junction vertical-channel tunneling field-effect transistor for low-voltage operation , 2010, 2010 IEEE Nanotechnology Materials and Devices Conference.
[14] S. Bala,et al. Design and analysis of electrostatic doped tunnel CNTFET for various process parameters variation , 2018, Superlattices and Microstructures.
[15] Massimo V. Fischetti,et al. Scaling MOSFETs to the Limit: A Physicists's Perspective , 2003 .
[16] W. Read,et al. Statistics of the Recombinations of Holes and Electrons , 1952 .
[17] Alok Naugarhiya,et al. RF & linearity distortion sensitivity analysis of DMG-DG-Ge pocket TFET with hetero dielectric , 2021, Microelectron. J..
[18] B. Raj,et al. Analysis of ION and Ambipolar Current for Dual-Material Gate-Drain Overlapped DG-TFET , 2016 .
[19] Yuan Taur,et al. Fundamentals of Modern VLSI Devices , 1998 .
[20] C. Hu,et al. Germanium-source tunnel field effect transistors with record high ION/IOFF , 2006, 2009 Symposium on VLSI Technology.
[21] Hongxia Liu,et al. Symmetric U-Shaped Gate Tunnel Field-Effect Transistor , 2017, IEEE Transactions on Electron Devices.
[22] B. Raj,et al. Design and Analysis of Dual Source Vertical Tunnel Field Effect Transistor for High Performance , 2019, Transactions on Electrical and Electronic Materials.
[23] K. Cheung. On the 60 mV/dec @300 K limit for MOSFET subthreshold swing , 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.
[24] Farooq Ahmad Khanday,et al. Spin field effect transistors and their applications: A survey , 2020, Microelectron. J..
[25] C. Shin,et al. Symmetric tunnel field-effect transistor (S-TFET) , 2015 .
[26] Y. Hao,et al. Comparative Study of Negative Capacitance Field-Effect Transistors with Different MOS Capacitances , 2019, Nanoscale Research Letters.
[27] A. Kranti,et al. Retention and Scalability Perspective of Sub-100-nm Double Gate Tunnel FET DRAM , 2017, IEEE Transactions on Electron Devices.
[28] H.C. de Graaff,et al. Bandgap narrowing in silicon bipolar transistors , 1977, IEEE Transactions on Electron Devices.
[29] Ru Huang,et al. Resistive-Gate Field-Effect Transistor: A Novel Steep-Slope Device Based on a Metal—Insulator—Metal—Oxide Gate Stack , 2014, IEEE Electron Device Letters.
[30] Adrian M. Ionescu,et al. Tunnel field-effect transistors as energy-efficient electronic switches , 2011, Nature.
[31] Hongxia Liu,et al. Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor , 2018, Nanoscale Research Letters.
[32] Haosu Luo,et al. Strain-mediated electric-field control of resistance in the La[sub 0.85]Sr[sub 0.15]MnO₃/0.7Pb(Mg[sub ⅓]Nb[sub ⅔])O₃-0.3PbTiO₃ structure , 2007 .
[33] J. Kim,et al. Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si , 2019, IEEE Transactions on Electron Devices.
[34] Christian Schmeiser,et al. On the Shockley-Read-Hall Model: Generation-Recombination in Semiconductors , 2007, SIAM J. Appl. Math..
[35] S. Dasgupta,et al. Demonstration of a Novel Two Source Region Tunnel FET , 2017, IEEE Transactions on Electron Devices.
[36] J. Hartmann,et al. A Novel Gate-Normal Tunneling Field-Effect Transistor With Dual-Metal Gate , 2018, IEEE Journal of the Electron Devices Society.
[37] Zhaonian Yang. Tunnel Field-Effect Transistor With an L-Shaped Gate , 2016, IEEE Electron Device Letters.
[38] I. Eisele,et al. Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in the δp+ Layer , 2004 .
[39] Brinda Bhowmick,et al. Optimization of ferroelectric tunnel junction TFET in presence of temperature and its RF analysis , 2019, Microelectron. J..
[40] Yee-Chia Yeo,et al. Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization , 2007 .
[41] Zhongyuan Yu,et al. Infrared Plasmonic Refractive Index Sensor with Ultra-High Figure of Merit Based on the Optimized All-Metal Grating , 2017, Nanoscale Research Letters.
[42] Junpeng Li,et al. Structure and Dielectric Property of High-k ZrO2 Films Grown by Atomic Layer Deposition Using Tetrakis(Dimethylamido)Zirconium and Ozone , 2019, Nanoscale Research Letters.
[43] K. Boucart,et al. Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric , 2007, IEEE Transactions on Electron Devices.
[44] W. Choi,et al. Hetero-Gate-Dielectric Tunneling Field-Effect Transistors , 2010, IEEE Transactions on Electron Devices.
[45] B. Raj,et al. Compact channel potential analytical modeling of DG-TFET based on Evanescent-mode approach , 2015 .
[46] B. Raj,et al. Analysis of ONOFIC Technique Using SiGe Heterojunction Double Gate Vertical TFET for Low Power Applications , 2020, Silicon.
[47] S. Stemmer,et al. BaTiO3/SrTiO3 heterostructures for ferroelectric field effect transistors , 2017 .
[48] F. Andrieu,et al. Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance , 2008, 2008 IEEE International Electron Devices Meeting.
[49] A. Raman,et al. An explicit surface potential, capacitance and drain current model for double-gate TFET , 2020 .
[50] Basab Das,et al. Noise behavior of ferro electric tunnel FET , 2020, Microelectron. J..
[51] Mitsuru Takenaka,et al. III–V/Ge MOSFETs and TFETs for ultra-low power logic LSIs , 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).
[52] Rajesh Saha,et al. Simulation study on ferroelectric layer thickness dependence RF/Analog and linearity parameters in ferroelectric tunnel junction TFET , 2021, Microelectron. J..
[53] J. Knoch,et al. A novel concept for field-effect transistors - the tunneling carbon nanotube FET , 2005, 63rd Device Research Conference Digest, 2005. DRC '05..
[54] K. Boucart,et al. Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[55] Byung-Gook Park,et al. 100-nm n-/p-channel I-MOS using a novel self-aligned structure , 2005 .
[56] Massimo Vanzi,et al. A physically based mobility model for numerical simulation of nonplanar devices , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..